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| preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) features the T7630 dual t1/e1 terminator consists of two independent, highly integrated, software-config- urable, full-featured short-haul transceiver/framers. the T7630 provides glueless interconnection from a t1/e1 line to a digital pcm system. minimal external clocks are needed. only a system clock/frame sync and a phase-locked line rate clock are required. sys- tem diagnostic and performance monitoring capabil- ity with integrated programmable test pattern generator/detector and loopback modes is provided. power requirements and package n single 5 v 5% supply. n low power: 375 mw per channel maximum. n 144-pin tqfp package. n operating temperature range: C40 c to +85 c. t1/e1 line interface features n full t1/e1 pulse template compliance. n receiver provides equalization for up to 11 db of loss. n digital clock and data recovery. n line coding: b8zs, hdb3, zcs, and ami. n line interface coupling and matching networks for t1 and e1 (120 w and 75 w ). t1/e1 framer features n supports t1 framing modes esf, d4, slc ? -96, t1dm dds. n supports g.704 basic and crc-4 multiframe for- mat e1 framing and procedures consistent with g.706. n supports unframed transmission format. n t1 signaling modes: transparent; esf 2-state, 4-state, and 16-state; d4 2-state and 4-state; slc -96 2-state, 4-state, 9-state and 16-state. e1 signaling modes: transparent and cas. n alarm reporting and performance monitoring per at & t, ansi *, and itu-t standards. n programmable, independent transmit and receive system interfaces at a 2.048 mhz, 4.096 mhz, or 8.192 mhz data rate. n system interface master mode for generation of system frame sync from the line source. n internal phase-locked loop (with external vcxo) for generation of system clock from the line source. facility data link features n hdlc or transparent modes. n automatic transmission and detection of ansi t1.403 fdl performance report message and bit- oriented codes. n 64-byte fifo in both transmit and receive direc- tions. microprocessor interface n 33 mhz, 8-bit data interface, no wait-states. n intel ? or motorola ? interface modes with multi- plexed or demultiplexed buses. n directly addressable control registers. applications n customer premises equipment csu/dsu, routers, digital pbx, channel banks (cb), base transceiver stations (bts-picocell), small switches, and digital subscriber loop access multiplexers (dslam). n loop/access dlc/idlc, dcs, bts (microcell/ macrocell), dslams, and multiplexers (terminal, synchronous/asynchronous, add drop). n central office digital switches, dcs, cb, access concentrators, remote switch modules (rsm), and dslams. n test equipment transmission/bert tester. * ansi is a registered trademark of american national standards institute, inc. ? intel is a registered trademark of intel corporation. ? motorola is a registered trademark of motorola, inc.
table of contents contents page preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) october 2000 2 lucent technologies inc. features ....................................................................................................................... ............................................ 1 t1/e1 line interface features.................................................................................................. ............................. 1 power requirements and package................................................................................................. ...................... 1 t1/e1 framer features .......................................................................................................... ............................... 1 facility data link features.................................................................................................... ................................ 1 microprocessor interface....................................................................................................... ................................ 1 applications ................................................................................................................... ........................................ 1 feature descriptions ........................................................................................................... ................................... 12 t1/e1 line interface features.................................................................................................. ........................... 12 t1/e1 framer features .......................................................................................................... ............................. 12 facility data link features.................................................................................................... .............................. 13 user-programmable microprocessor interface ..................................................................................... .............. 13 functional description ......................................................................................................... ................................... 14 pin information ................................................................................................................ ....................................... 18 line interface unit: block diagram ............................................................................................. ............................ 25 line interface unit: receive ................................................................................................... ................................ 25 data recovery.................................................................................................................. ................................... 25 jitter accommodation and jitter transfer without the jitter attenuator ......................................................... ..... 26 receive line interface configuration modes ..................................................................................... ................. 26 line interface unit: transmit .................................................................................................. ................................ 32 output pulse generation........................................................................................................ ............................. 32 liu transmitter configuration modes ............................................................................................ ..................... 33 liu transmitter alarms ......................................................................................................... .............................. 33 dsx-1 transmitter pulse template and specifications ............................................................................ .......... 34 cept transmitter pulse template and specifications ............................................................................. .......... 36 line interface unit: jitter attenuator ......................................................................................... .............................. 37 generated (intrinsic) jitter................................................................................................... ................................ 37 jitter transfer function ....................................................................................................... ................................ 37 jitter accommodation........................................................................................................... ............................... 38 jitter attenuator enable (transmit or receive path)............................................................................ ............... 38 line interface unit: loopbacks ................................................................................................. .............................. 41 full local loopback (flloop)................................................................................................... ........................ 41 remote loopback (rloop) ........................................................................................................ ....................... 41 digital local loopback (dlloop) ................................................................................................ ...................... 41 line interface unit: other features ............................................................................................ ............................ 41 liu powerdown (pwrdn) .......................................................................................................... ........................ 41 loss of framer receive line clock (lofrmrlck pin).............................................................................. ....... 41 in-circuit testing and driver high-impedance state (3-state )......................................................................... 41 liu delay values............................................................................................................... .................................. 42 sysck reference clock.......................................................................................................... .............................. 42 line interface unit: line interface networks................................................................................... ........................ 43 liu-framer interface ........................................................................................................... ................................... 46 liu-framer physical interface.................................................................................................. ........................... 46 interface mode and line encoding............................................................................................... ....................... 47 ds1: alternate mark inversion (ami)............................................................................................ ....................... 48 ds1: zero code suppression (zcs)............................................................................................... .................... 48 cept: high-density bipolar of order 3 (hdb3)................................................................................... ............... 49 frame formats .................................................................................................................. ..................................... 49 t1 framing structures.......................................................................................................... ............................... 49 lucent technologies inc. 3 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) table of contents (continued) contents page t1 loss of frame alignment (lfa)............................................................................................... .......................57 t1 frame recovery alignment algorithms ......................................................................................... .................58 t1 robbed-bit signaling ........................................................................................................ ............................. 59 cept 2.048 basic frame, crc-4 time slot 0, and signaling time slot 16 multiframe structures ....................61 cept 2.048 basic frame structure............................................................................................... ......................62 cept loss of basic frame alignment (lfa)....................................................................................... ................63 cept loss of frame alignment recovery algorithm ................................................................................ ..........63 cept time slot 0 crc-4 multiframe structure.................................................................................... ...............64 cept loss of crc-4 multiframe alignment (lts0mfa) .............................................................................. ......65 cept loss of crc-4 multiframe alignment recovery algorithms.................................................................... ..66 cept time slot 16 multiframe structure......................................................................................... ....................70 cept loss of time slot 16 multiframe alignment (lts16mfa) ...................................................................... ...71 cept loss of time slot 16 multiframe alignment recovery algorithm .............................................................. 71 cept time slot 0 fas/not fas control bits ..................................................................................... .................71 fas/not fas si- and e-bit source............................................................................................... .....................71 not fas a-bit (cept remote frame alarm) sources ................................................................................ ......72 not fas sa-bit sources ......................................................................................................... ...........................72 sa facility data link access................................................................................................... .............................73 not fas sa stack source and destination........................................................................................ ................74 cept time slot 16 x0x2 control bits ........................................................................................... ..................76 signaling access............................................................................................................... ......................................76 transparent signaling.......................................................................................................... ................................76 ds1: robbed-bit signaling ...................................................................................................... ............................76 cept: time slot 16 signaling................................................................................................... ..............................77 auxiliary framer i/o timing .................................................................................................... ................................78 alarms and performance monitoring.............................................................................................. .........................81 interrupt generation........................................................................................................... ..................................81 alarm definition............................................................................................................... .....................................81 event counters definition ...................................................................................................... ..............................86 loopback and transmission modes ................................................................................................ ....................88 line test patterns............................................................................................................. ...................................91 automatic and on-demand commands ............................................................................................... ...............95 receive facility data link interface........................................................................................... ..........................97 transmit facility data link interface.......................................................................................... ........................103 hdlc operation ................................................................................................................. ...............................104 transparent mode............................................................................................................... ...............................107 diagnostic modes ............................................................................................................... ...............................108 phase-lock loop circuit ........................................................................................................ ...............................110 framer-system (chi) interface .................................................................................................. ...........................112 ds1 modes ...................................................................................................................... ..................................112 cept modes..................................................................................................................... .................................112 receive elastic store.......................................................................................................... ...............................112 transmit elastic store......................................................................................................... ...............................112 concentration highway interface ................................................................................................ ..........................112 chi parameters ................................................................................................................. ................................113 chi frame timing............................................................................................................... ...............................115 chi offset programming......................................................................................................... ...........................118 jtag boundary-scan specification ............................................................................................... .......................120 principle of the boundary scan................................................................................................. .........................120 contents page preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) october 2000 4 lucent technologies inc. table of contents (continued) test access port controller.................................................................................................... ........................... 121 instruction register ........................................................................................................... ................................ 123 boundary-scan register ......................................................................................................... .......................... 124 bypass register................................................................................................................ .............................. 124 idcode register ................................................................................................................ .............................. 124 3-state procedures ............................................................................................................. .............................. 124 microprocessor interface ....................................................................................................... ............................... 125 overview ....................................................................................................................... .................................... 125 microprocessor configuration modes............................................................................................. ................... 125 microprocessor interface pinout definitions.................................................................................... .................. 126 microprocessor clock (mpclk) specifications.................................................................................... ............. 127 microprocessor interface register address map .................................................................................. ............ 127 i/o timing..................................................................................................................... ..................................... 127 reset .......................................................................................................................... .......................................... 134 hardware reset (pin 43/139).................................................................................................... ........................ 134 software reset/software restart ................................................................................................ ...................... 134 register architecture .......................................................................................................... .................................. 135 global register architecture................................................................................................... .............................. 139 global register structure ...................................................................................................... ............................... 140 primary block interrupt status register (greg0) ................................................................................ ............ 140 primary block interrupt enable register (greg1) ................................................................................ ........... 140 global loopback control register (greg2) ....................................................................................... ............. 141 global loopback control register (greg3) ....................................................................................... ............. 141 global control register (greg4) ................................................................................................ ..................... 142 device id and version registers (greg5greg7) .................................................................................. .... 142 line interface unit (liu) register architecture................................................................................ ..................... 143 line interface alarm register .................................................................................................. ............................. 144 alarm status register (liu_reg0)............................................................................................... .................... 144 line interface alarm interrupt enable register ................................................................................. ................... 144 alarm interrupt enable register (liu_reg1) ..................................................................................... .............. 144 line interface control registers ............................................................................................... ............................ 145 liu control register (liu_reg2) ................................................................................................ ..................... 145 liu control register (liu_reg3) ................................................................................................ ..................... 145 liu control register (liu_reg4) ................................................................................................ ..................... 146 liu configuration register (liu_reg5) .......................................................................................... ................. 147 liu configuration register (liu_reg6) .......................................................................................... ................. 147 framer register architecture ................................................................................................... ............................ 148 framer status/counter registers................................................................................................ ...................... 149 fdl register architecture ...................................................................................................... .............................. 190 fdl parameter/control registers (80080e; e00e0e) ............................................................................. ..... 191 register maps .................................................................................................................. .................................... 198 global registers............................................................................................................... ................................. 198 line interface unit parameter/control and status registers ..................................................................... ....... 198 framer parameter/control registers (read-write)................................................................................ ........... 199 receive framer signaling registers (read-only) ................................................................................. ........... 201 framer unit parameter register map ............................................................................................. ................. 202 transmit signaling registers (read/write) ...................................................................................... ................. 205 facility data link parameter/control and status registers (read-write)........................................................ 206 absolute maximum ratings....................................................................................................... .......................... 207 lucent technologies inc. 5 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) table of contents (continued) contents page operating conditions ........................................................................................................... ................................ 207 handling precautions ........................................................................................................... .................................207 electrical characteristics ..................................................................................................... ..................................208 logic interface characteristics................................................................................................ ...........................208 power supply bypassing ......................................................................................................... .............................208 outline diagram ................................................................................................................ ....................................209 144-pin tqfp ................................................................................................................... .................................209 ordering information ........................................................................................................... ..................................210 figures page figure 1. T7630 block diagram (one of two channels) ............................................................................ .............14 figure 2. T7630 block diagram: receive section (one of two channels) ........................................................... ..16 figure 3. T7630 block diagram: transmit section (one of two channels).......................................................... ...17 figure 4. pin assignment ....................................................................................................... .................................18 figure 5. block diagram of line interface unit: single channel ................................................................. ............25 figure 6. t1/ds1 receiver jitter accommodation without jitter attenuator....................................................... ....30 figure 7. t1/ds1 receiver jitter transfer without jitter attenuator............................................................ ............30 figure 8. cept/e1 receiver jitter accommodation without jitter attenuator ...................................................... ..31 figure 9. cept/e1 receiver jitter transfer without jitter attenuator ........................................................... ..........31 figure 10. dsx-1 isolated pulse template ....................................................................................... ......................34 figure 11. itu-t g.703 pulse template.......................................................................................... ........................36 figure 12. t1/ds1 receiver jitter accommodation with jitter attenuator ......................................................... .....39 figure 13. t1/ds1 jitter transfer of the jitter attenuator ..................................................................... ...................39 figure 14. cept/e1 receiver jitter accommodation with jitter attenuator........................................................ ....40 figure 15. cept/e1 jitter transfer of the jitter attenuator .................................................................... .................40 figure 16. line termination circuitry .......................................................................................... ............................43 figure 17. T7630 line interface unit approximate equivalent analog i/o circuits ................................................ .45 figure 18. block diagram of framer line interface.............................................................................. ...................46 figure 19. transmit framer tlck to tnd, tpd and receive framer rnd, rpd to rlck timing ........................47 figure 20. t1 frame structure .................................................................................................. ..............................50 figure 21. t1 transparent frame structure ...................................................................................... ......................51 figure 22. T7630 facility data link access timing of the transmit and receive framer sections........................53 figure 23. fs pattern slc -96 superframe format .................................................................................................53 figure 24. itu 2.048 basic frame, crc-4 multiframe, and channel associated signaling multiframe structures ..................................................................................................................... ........................................61 figure 25. cept transparent frame structure.................................................................................... ...................62 figure 26. receive crc-4 multiframe search algorithm using the 100 ms internal timer ...................................67 figure 27. receive crc-4 multiframe search algorithm for automatic, crc-4/non-crc-4 equipment interworking as defined by itu (from itu rec. g.706, annex b.2.2 - 1991) ....................................69 figure 28. facility data link access timing of the transmit and receive framer sections in the cept mode.....73 figure 29. transmit and receive sa stack accessing protocol.................................................................... ..........75 figure 30. timing specification for rfrmck, rfrmdata, and rfs in ds1 mode...............................................78 figure 31. timing specification for tfs, tlck, and tpd in ds1 mode ............................................................. ....78 figure 32. timing specification for rfrmck, rfrmdata, and rfs in cept mode ............................................79 figure 33. timing specification for rfrmck, rfrmdata, rfs, and rssfs in cept mode ..............................79 figure 34. timing specification for rcrcmfs in cept mode ....................................................................... .......80 figure 35. timing specification for tfs, tlck, and tpd in cept mode ............................................................ ..80 figure 36. timing specification for tfs, tlck, tpd, and tssfs in cept mode .................................................80 figure 37. timing specification for tfs, tlck, tpd, and tcrcmfs in cept mode ...........................................81 table of contents (continued) figures page preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) october 2000 6 lucent technologies inc. figure 38. relation between rlck1 and interrupt (pin 99)....................................................................... ............ 81 figure 39. timing for generation of lopllck (pin 39/143) ....................................................................... ........... 83 figure 40. the t and v reference points for a typical cept e1 application...................................................... .. 85 figure 41. loopback and test transmission modes................................................................................ ............... 90 figure 42. 20-stage shift register used to generate the quasi-random signal.................................................. 91 figure 43. 15-stage shift register used to generate the pseudorandom signal ................................................. 92 figure 44. T7630 facility data link access timing of the transmit and receive framer sections ....................... 97 figure 45. block diagram for the receive facility data link interface .......................................................... ......... 98 figure 46. block diagram for the transmit facility data link interface......................................................... ........ 103 figure 47. local loopback mode ................................................................................................. ........................ 109 figure 48. remote loopback mode ................................................................................................ ..................... 109 figure 49. T7630 phase detector circuitry ...................................................................................... .................... 111 figure 50. nominal concentration highway interface timing (for frm_pr43 bit 0bit 2 = 100 (binary)) ......... 115 figure 51. chidts mode concentration highway interface timing .................................................................. .. 116 figure 52. associated signaling mode concentration highway interface timing ................................................ 117 figure 53. chi timing with asm and chidts enabled.............................................................................. ......... 117 figure 54. tchidata and rchidata to chick relationship with cms = 0 (cex = 3 and cer = 4, respectively) ............................................................................................ ................... 118 figure 55. receive chi (rchidata) timing ....................................................................................... ................. 119 figure 56. transmit chi (tchidata) timing...................................................................................... .................. 119 figure 57. block diagram of the T7630's boundary-scan test logic ............................................................... ... 120 figure 58. bs tap controller state diagram..................................................................................... ................... 121 figure 59. mode 1read cycle timing (mpmode = 0, mpmux = 0) ............................................................... 130 figure 60. mode 1write cycle timing (mpmode = 0, mpmux = 0) ............................................................... 130 figure 61. mode 2read cycle timing (mpmode = 0, mpmux = 1) ............................................................... 131 figure 62. mode 2write cycle timing (mpmode = 0, mpmux = 1) ............................................................... 131 figure 63. mode 3read cycle timing (mpmode = 1, mpmux = 0) ............................................................... 132 figure 64. mode 3write cycle timing (mpmode = 1, mpmux = 0) ............................................................... 132 figure 65. mode 4read cycle timing (mpmode = 1, mpmux = 1) ............................................................... 133 figure 66. mode 4write cycle timing (mpmode = 1, mpmux = 1) ............................................................... 133 lucent technologies inc. 7 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) table of contents (continued) table page table 1. pin descriptions-channel 1 and channel 2............................................................................. .................19 table 2. pin descriptions-global .............................................................................................. ..............................23 table 3. digital loss of signal standard select............................................................................... .......................27 table 4. lossd and rcvais control configurations (not valid during loopback modes) ..................................27 table 5. t1/ds1 liu receiver specifications................................................................................... ......................28 table 6. cept liu receiver specifications ..................................................................................... ......................29 table 7. transmit line interface short-haul equalizer/rate control ............................................................ ..........32 table 8. dsx-1 pulse template corner points (from cb119, t1.102) .............................................................. .....35 table 9. ds1 transmitter specifications ....................................................................................... ..........................35 table 10. cept transmitter specifications ..................................................................................... .......................37 table 11. loopback control.................................................................................................... ................................41 table 12. sysck (16x, cksel = 1) timing specifications........................................................................ ............42 table 13. sysck (1x, cksel = 0) timing specifications......................................................................... .............42 table 14. termination components by application............................................................................... ..................44 table 15. ami encoding ........................................................................................................ .................................48 table 16. ds1 zcs encoding.................................................................................................... .............................48 table 17. ds1 b8zs encoding................................................................................................... ............................49 table 18. itu hdb3 coding ..................................................................................................... ..............................49 table 19. t-carrier hierarchy................................................................................................. .................................49 table 20. d4 superframe format ................................................................................................ ...........................52 table 21. dds channel-24 format ............................................................................................... .........................52 table 22. slc -96 data link block format ..................................................................................................... ........54 table 23. slc -96 line switch message codes .................................................................................................. ...55 table 24. transmit and receive slc -96 stack structure.......................................................................................55 table 25. extended superframe (esf) structure................................................................................. ..................56 table 26. t1 loss of frame alignment criteria ................................................................................. .....................57 table 27. t1 frame alignment procedures ....................................................................................... .....................58 table 28. robbed-bit signaling options........................................................................................ .........................59 table 29. slc -96 9-state signaling format ................................................................................................... ........59 table 30. 16-state signaling format ........................................................................................... ...........................60 table 31. allocation of bits 1 to 8 of the fas frame and the not fas frame .................................................... ..62 table 32. itu crc-4 multiframe structure...................................................................................... .......................64 table 33. itu cept time slot 16 channel associated signaling multiframe structure ........................................70 table 34. transmit and receive sa stack structure............................................................................. ..................74 table 35. associated signaling mode chi 2-byte time-slot format for ds1 frames ...........................................77 table 36. associated signaling mode chi 2-byte time-slot format for stuffed channels....................................77 table 37. associated signaling mode chi 2-byte time-slot format for cept .....................................................7 7 table 38. red alarm or loss of frame alignment conditions..................................................................... ...........82 table 39. remote frame alarm conditions....................................................................................... .....................82 table 40. alarm indication signal conditions .................................................................................. .......................82 table 41. sa6 bit coding recognized by the receive framer-asynchronous bit stream .....................................84 table 42. sa6 bit coding recognized by the receive framer-synchronous bit stream .......................................85 table 43. auxp synchronization and clear sychronization process ............................................................... .....85 table 44. event counters definition ........................................................................................... ............................86 table 45. summary of the deactivation of sstsslb and sstsllb modes as a function of activating the primary loopback modes ....................................................................................... ...................89 table 46. register frm_pr69 test patterns..................................................................................... ....................92 table 47. register frm_pr70 test patterns..................................................................................... ....................93 table 48. automatic enable commands ........................................................................................... .....................95 table 49. on-demand commands .................................................................................................. .......................96 table of contents (continued) table page preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) october 2000 8 lucent technologies inc. table 50. receive ansi code .......................................................................................................................... ..... 99 table 51. performance report message structure................................................................................ ................ 99 table 52. fdl performance report message field definition..................................................................... ........ 100 table 53. octet contents and definition ....................................................................................... ....................... 100 table 54. receive status of frame byte........................................................................................ ...................... 101 table 55. hdlc frame format................................................................................................... ......................... 104 table 56. receiver operation in transparent mode.............................................................................. ............... 108 table 57. summary of the T7630s concentration highway interface parameters .............................................. 113 table 58. programming values for toff[2:0] and roff[2:0] when cms = 0 .................................................... 118 table 59. tap controller states in the data register branch................................................................... ........... 122 table 60. tap controller states in the instruction register branch............................................................ ......... 122 table 61. T7630s boundary-scan instructions .................................................................................. ................. 123 table 62. idcode register..................................................................................................... ............................ 124 table 63. microprocessor configuration modes .................................................................................. ................ 125 table 64. mode [14] microprocessor pin definitions ........................................................................... ............. 126 table 65. microprocessor input clock specifications ........................................................................... ............... 127 table 66. T7630 register address map .......................................................................................... .................... 127 table 67. microprocessor interface i/o timing specifications .................................................................. ........... 128 table 68. register summary .................................................................................................... ........................... 135 table 69. global register set (0x0000x008) ................................................................................... ................ 139 table 70. primary block interrupt status register (greg0) (000) ............................................................... ...... 140 table 71. primary block interrupt enable register (greg1) (001) ............................................................... ..... 140 table 72. global loopback control register (greg2) (002) ...................................................................... ........ 141 table 73. global loopback control register (greg3) (003) ...................................................................... ........ 141 table 74. global control register (greg4) (004) ............................................................................... ............... 142 table 75. device id and version registers (greg5greg7) (005007) ...................................................... 142 table 76. line interface units register set* ((40040f); (a00a0f))........................................................... ... 143 table 77. liu alarm status register (liu_reg0) (400, a00) ..................................................................... ........ 144 table 78. liu alarm interrupt enable register (liu_reg1) (401, a01) ........................................................... .. 144 table 79. liu control register (liu_reg2) (402, a02) .......................................................................... ............ 145 table 80. liu control register (liu_reg3) (403, a03) .......................................................................... ............ 145 table 81. lossd and rcvais control configurations (not valid during loopback modes) (from table 3) ...... 146 table 82. liu register (liu_reg4) (404, a04).................................................................................. ................. 146 table 83. liu configuration register (liu_reg5) (405, a05) .................................................................... ........ 147 table 84. loopback control .................................................................................................... ............................. 147 table 85. liu configuration register (liu_reg6) (406, a06) .................................................................... ........ 147 table 86. transmit line interface short-haul equalizer/rate control (from table 6)........................................... 1 48 table 87. framer status and control blocks address range (hexadecimal)...................................................... 14 8 table 88. interrupt status register (frm_sr0) (600; c00) ...................................................................... .......... 149 table 89. facility alarm condition register (frm_sr1) (601; c01) .............................................................. ..... 150 table 90. remote end alarm register (frm_sr2) (602; c02) ...................................................................... .... 151 table 91. facility errored event register-1 (frm_sr3) (603; c03) .............................................................. ..... 152 table 92. facility event register-2 (frm_sr4) (604; c04) ...................................................................... .......... 153 table 93. exchange termination and exchange termination remote end interface status register (frm_sr5) (605; c05) ............................................................................. ......... 154 table 94. network termination and network termination remote end interface status register (frm_sr6) (606; c06) ............................................................................. ......... 155 table 95. facility event register (frm_sr7) (607; c07) ........................................................................ ........... 156 table 96. bipolar violation counter registers (frm_sr8frm_sr9) ((608609); (c08c09)) .................. 156 table 97. framing bit error counter registers (frm_sr10frm_sr11) ((60a60b); (c0ac0b)) ........... 156 lucent technologies inc. 9 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) table of contents (continued) table page table 98. crc error counter registers (frm_sr12frm_sr13) ((60c60d); (c0cc0d))......................157 table 99. e-bit counter registers (frm_sr14frm_sr15) ((60e60f); (c0ec0f))................................157 table 100. crc-4 errors at nt1 from nt2 counter registers (frm_sr16frm_sr17) ((610611); (c10c11)) ..................................................................................................................... ..................................157 table 101. e bit at nt1 from nt2 counter (frm_sr18frm_sr19) ((612613); (c12c13)) ...................157 table 102. et errored seconds counter (frm_sr20frm_sr21) ((614615); (c14c15)) ......................158 table 103. et bursty errored seconds counter (frm_sr22frm_sr23) ((616617); (c16c17)) ...........158 table 104. et severely errored seconds counter (frm_sr24frm_sr25) ((618619); (c18c19))........158 table 105. et unavailable seconds counter (frm_sr26frm_sr27) ((61a61b); (c1ac1b)) ..............158 table 106. et-re errored seconds counter (frm_sr28frm_sr29) ((61c61d); (c1cc1d)) ..............158 table 107. et-re bursty errored seconds counter (frm_sr30frm_sr31) ((61e61f); (c1ec1f)) ....158 table 108. et-re severely errored seconds counter (frm_sr32frm_sr33) ((620621); (c20c21)) ..158 table 109. et-re unavailable seconds counter (frm_sr34frm_sr35) ((622623); (c22c23)) ..........159 table 110. nt1 errored seconds counter (frm_sr36frm_sr37) ((624625); (c24c25)) ....................159 table 111. nt1 bursty errored seconds counter (frm_sr38frm_sr39) ((626627); (c26c27)) .........159 table 112. nt1 severely errored seconds counter (frm_sr40frm_sr41) ((628629); (c28c29)) .....159 table 113. nt1 unavailable seconds counter (frm_sr42frm_sr43) ((62a62b); (c2ac2b)) ............159 table 114. nt1-re errored seconds counter (frm_sr44frm_sr45) ((62c62d); (c2cc2d))............159 table 115. nt1-re bursty errored seconds counter (frm_sr46frm_sr47) ((62e62f); (c2ec2f))..159 table 116. nt1-re severely errored seconds counter (frm_sr48frm_sr49 ((630631); (c30c31)) ..................................................................................................................... ..................................160 table 117. nt1-re unavailable seconds counter (frm_sr50frm_sr51) ((632633); (c32c33)) .......160 table 118. receive not-fas ts0 register (frm_sr52) (634; c34) ................................................................. 160 table 119. receive sa register (frm_sr53) (635; c35) .......................................................................... .........160 table 120. slc -96 fdl receive stack (frm_sr54frm_sr63) ((63663f); (c36c3f)) ........................161 table 121. cept sa receive stack (frm_sr54frm_sr63) ((63663f); (c36c3f)) .............................161 table 122. transmit framer ansi performance report message status register structure ..............................162 table 123. received signaling registers: ds1 format (frm_rsr0frm_rsr23) ((640658); (c40c58)) ..................................................................................................................... ..................................162 table 124. receive signaling registers: cept format (frm_rsr0frm_rsr31) ((64065f); (c40c5f)) ..................................................................................................................... ..................................162 table 125. summary of interrupt group enable registers (frm_pr0frm_pr7) ((660667); (c60c67)) ..................................................................................................................... ..................................163 table 126. primary interrupt group enable register (frm_pr0) (660; c60) .....................................................16 4 table 127. interrupt enable register (frm_pr1) (661; c61)..................................................................... .........165 table 128. interrupt enable register (frm_pr2) (662; c62)..................................................................... .........165 table 129. interrupt enable register (frm_pr3) (663; c63)..................................................................... .........165 table 130. interrupt enable register (frm_pr4) (664; c64)..................................................................... .........165 table 131. interrupt enable register (frm_pr5) (665; c65)..................................................................... .........165 table 132. interrupt enable register (frm_pr6) (666; c66)..................................................................... .........165 table 133. interrupt enable register (frm_pr7) (667; c67)..................................................................... .........165 table 134. framer mode bits decoding (frm_pr8) (668; c68) ..................................................................... ....166 table 135. line code option bits decoding (frm_pr8) (668; c68) ................................................................ ..166 table 136. crc option bits decoding (frm_pr9) (669, c69) ...................................................................... .....167 table 137. alarm filter register (frm_pr10) (66a; c6a) ........................................................................ ..........167 table 138. errored event threshold definition................................................................................. ....................168 table 139. errored second threshold register (frm_pr11) (66b; c6b) ..........................................................16 8 table 140. severely errored second threshold registers (frm_pr12frm_pr13) ((66c66d; c6cc6d)) ...................................................................................................................... .................................168 table 141. et1 errored event enable register (frm_pr14) (66e; c6e)...........................................................1 69 table of contents (continued) table page preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) october 2000 10 lucent technologies inc. table 142. et1 remote end errored event enable register (frm_pr15) (66f; c6f) ..................................... 169 table 143. nt1 errored event enable register (frm_pr16) (670; c70)........................................................... 1 69 table 144. nt1 remote end errored event enable registers (frm_pr17frm_pr18) ((671672);(c71c72))...................................................................................... 169 table 145. automatic ais to the system and automatic loopback enable register (frm_pr19) (673; c73) .. 170 table 146. transmit test pattern to the line enable register (frm_pr20) (674; c74) ..................................... 170 table 147. framer fdl control command register (frm_pr21) (675; c75) ................................................... 171 table 148. framer transmit line idle code register (frm_pr22) (676; c76)................................................... 171 table 149. framer system stuffed time-slot code register (frm_pr23) (677; c77) ...................................... 171 table 150. primary time-slot loopback address register (frm_pr24) (678; c78) ......................................... 172 table 151. loopback decoding of bits lbc[2:0] in frm_pr24, bits 75 ........................................................ 17 2 table 152. secondary time-slot loopback address register (frm_pr25) (679; c79) .................................... 173 table 153. loopback decoding of bits lbc[1:0] in frm_pr25, bits 65 ......................................................... 17 3 table 154. framer reset and transparent mode control register (frm_pr26) (67a, c7a)............................. 174 table 155. transmission of remote frame alarm and cept automatic transmission of a bit = 1 control register (frm_pr27) (67b, c7b)............................................... 175 table 156. cept automatic transmission of e bit = 0 control register (frm_pr28) (67c; c7c).................... 176 table 157. sa4sa8 source register (frm_pr29) (67d; c7d)...................................................................... .177 table 158. sa bits source control for bit 5bit 7 in frm_pr29 ................................................................. ...... 177 table 159. sa4sa8 control register (frm_pr30) (67e; c7e)..................................................................... .. 178 table 160. sa transmit stack (frm_pr31frm_pr40) ((67f688); (c7fc88)) ....................................... 178 table 161. slc -96 transmit stack (frm_pr31frm_pr40) ((67f688); (c7fc88)) ............................... 179 table 162. transmit slc -96 fdl format ............................................................................................................ 179 table 163. cept time slot 16 x-bit remote multiframe alarm and ais control register (frm_pr41)(689; c89) .................................................................................. .......... 179 table 164. framer exercise register (frm_pr42) (68a; c8a)..................................................................... ..... 180 table 165. framer exercises, frm_pr42 bit 5bit 0 (68a; c8a).................................................................. ... 180 table 166. ds1 system interface control and cept fdl source control register (frm_pr43) (68b; c8b) .. 181 table 167. signaling mode register (frm_pr44) (68c; c8c)...................................................................... ..... 182 table 168. chi common control register (frm_pr45) (68d; c8d) ................................................................. 1 83 table 169. chi common control register (frm_pr46) (68e; c8e) ................................................................. 1 84 table 170. chi transmit control register (frm_pr47) (68f; c8f) ................................................................ ... 184 table 171. chi receive control register (frm_pr48) (690; c90) ................................................................. ... 184 table 172. chi transmit time-slot enable registers (frm_pr49frm_pr52) ((691694); (c91c94))... 185 table 173. chi receive time-slot enable registers (frm_pr53frm_pr56) ((695698); (c95c98)) ... 185 table 174. chi transmit highway select registers (frm_pr57frm_pr60) ((69969c); (c99c9c)) .... 185 table 175. chi receive highway select registers (frm_pr61frm_pr64) ((69d6a0); (c9dca0)) .... 186 table 176. chi transmit control register (frm_pr65) (6a1; ca1)................................................................ ... 186 table 177. chi receive control register (frm_pr66) (6a2; ca2) ................................................................. .. 186 table 178. auxiliary pattern generator control register (frm_pr69) (6a5; ca5) ............................................ 187 table 179. pattern detector control register (frm_pr70) (6a6; ca6) ............................................................ .188 table 180. transmit signaling registers: ds1 format (frm_tsr0frm_tsr23) ((6e06f7); (ce0cf7)) ................................................................................. 189 table 181. transmit signaling registers: cept format (frm_tsr0frm_tsr31) ((6e06ff); (ce0cff))................................................................................. 189 table 182. fdl register set (80080e); (e00e0e) .............................................................................. ......... 190 table 183. fdl configuration control register (fdl_pr0) (800; e00) ............................................................ .. 191 table 184. fdl control register (fdl_pr1) (801; e01) .......................................................................... .......... 191 table 185. fdl interrupt mask control register (fdl_pr2) (802; e02) ........................................................... .192 table 186. fdl transmitter configuration control register (fdl_pr3) (803; e03) ........................................... 193 lucent technologies inc. 11 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) table of contents (continued) table page table 187. fdl transmitter fifo register (fdl_pr4) (804; e04)................................................................. .....193 table 188. fdl transmitter idle character register (fdl_pr5) (805; e05) ....................................................... 193 table 189. fdl receiver interrupt level control register (fdl_pr6) (806; e06) ..............................................194 table 190. fdl register fdl_pr7............................................................................................... .......................194 table 191. fdl receiver match character register (fdl_pr8) (808; e08) .......................................................19 4 table 192. fdl transparent control register (fdl_pr9) (809; e09) .............................................................. ...195 table 193. fdl transmit ansi esf bit codes (fdl_pr10) (80a; e0a).............................................................195 table 194. fdl interrupt status register (clear on read) (fdl_sr0) (80b; e0b).............................................196 table 195. fdl transmitter status register (fdl_sr1) (80c; e0c)............................................................... ....197 table 196. fdl receiver status register (fdl_sr2) (80d; e0d) .................................................................. ....197 table 197. receive ansi fdl status register (fdl_sr3) (80e; e0e) ..............................................................197 table 198. fdl receiver fifo register (fdl_sr4) (807; e07) .................................................................... .....197 table 199. global register set................................................................................................ .............................198 table 200. line interface unit register set ................................................................................... .......................198 table 201. framer unit status register map .................................................................................... ...................199 table 202. receive signaling registers map .................................................................................... ...................201 table 203. framer unit parameter register map ................................................................................. ................202 table 204. transmit signaling registers map ................................................................................... ...................205 table 205. facility data link register map .................................................................................... ......................206 table 206. esd threshold voltage.............................................................................................. .........................207 table 207. logic interface characteristics (t a = C40 c to +85 c, v dd = 5.0 v 5%, v ss = 0).........................208 preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 12 lucent technologies inc. lucent technologies inc. feature descriptions n two independent t1/e1 channels each consisting of a t1/e1 short-haul line interface and a t1/e1 framer with hdlc formatting on the facility data link inter- face. n memory-mapped read and write registers. n maskable interrupt events. n hardware and software resets. n onboard software-selectable pseudorandom test pattern generator and detector for line performance monitoring. n 3-state outputs. n single 5 v 5% supply. n low power consumption: 750 mw max. t1/e1 line interface features n transmitter includes transmit encoder (b8zs or hdb3), pulse shaping, and line driver. n five pulse equalization settings for template compli- ance at dsx cross connect. n receive includes equalization, digital clock and data recovery (immune to false lock), and receive decoder. n cept/e1 interference immunity as required by g.703. n transmit jitter <0.02 ui. n receive generated jitter <0.05 ui. n jitter attenuator selectable for use in transmit or receive path. jitter attenuation characteristics are data pattern independent. n for use with 100 w ds1 twisted-pair, 120 w e1 twisted-pair, and 75 w e1 coaxial cable. n common transformer for transmit/receive. n analog los alarm for signals less than C18 db for greater than 1 ms or 10-bit to 255-bit symbol periods (selectable). n digital los alarm for 100 zeros (ds1) or 255 zeros (e1). n diagnostic loopback modes. n compliant with at&t cb119(10/79); itu g.703(88), g.732(88), g.735-9(88), g.823-4(3/93), i.431(3/93); ansi t1.102(93), t1. 408(90); etsi, ets-300-166(8/93), tbr12(12/93, 1/ 96), tbr13(1/96); tr-tsy-000009(5/86), tsy- 000170(1/93), gr-253-core(12/95), gr-499- core(12/95), gr-820-core(11/94), gr-1244- core(6/95). t1/e1 framer features n framing formats: compliant with t1 standards ansi t1.231 (1993), at&t tr54016, at&t tr62411 (1998). unframed, transparent transmission in t1 and e1 formats. ds1 extended superframe (esf). ds1 superframe (sf): d4; slc -96; t1dm dds; t1dm dds with fdl access. ds1 independent transmit and receive framing modes when using the esf and d4 formats. compliant with itu cept framing recommenda- tion: 1. g.704 and g.706 basic frame format. 2. g.704 section 2.3.3.4 and g.706 section 4.2: crc-4 multiframe search algorithm. 3. g.706 annex b: crc-4 multiframe search algo- rithm with 400 ms timer for interworking of crc-4 and non-crc-4 equipment. 4. g.706 section 4.3.2 note 2: monitoring of 915 crc-4 checksum errors for loss of frame state. n framer line codes: ds1: alternate mark inversion (ami); binary eight zero code suppression (b8zs); per-channel zero code suppression; decoding bipolar violation monitor; monitoring of eight or fifteen bit intervals without positive or negative pulses error indica- tion. ds1 independent transmit and receive path line code formats when using ami/zcs and b8zs coding. itu-cept: ami; high-density bipolar 3 (hdb3) encoding and decoding bipolar violation monitor- ing, monitoring of four bit intervals without positive or negative pulses error indication. single-rail option. lucent technologies inc. 13 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. feature descriptions (continued) n signaling: ds1: extended superframe 2-state, 4-state, and 16-state per-channel robbed bit. ds1: d4 superframe 2-state and 4-state per- channel robbed bit. ds1: slc -96 superframe 2-state, 4-state, 9-state, and 16-state per-channel robbed bit. ds1: channel-24 message-oriented signaling. itu cept: channel associated signaling (cas). transparent (all data channels). n alarm reporting, performance monitoring, and main- tenance: ansi t1.403-1995, at&t tr 54016, and itu g.826 standard error checking. error and status counters. bipolar violations. errored frame alignment signals. errored crc checksum block. cept: received e bit = 0. errored, severely errored, and unavailable sec- onds. selectable errored event monitoring for errored and severely errored seconds processing with programmable thresholds for errored and severely errored second monitoring. cept: selectable automatic transmission of e bit to the line. cept: sa6 coded remote end crc-4 error e bit = 0 events. programmable automatic and on-demand alarm transmission. 1. automatic transmission of remote frame alarm to the line while in loss of frame alignment state. 2. automatic transmission of alarm indication sig- nal (ais) to the system while in loss of frame alignment state. multiple loopback modes. optional automatic line and payload loopback activate and deactivate modes. cept nailed-up connect loopback and cept nailed-up broadcast transmission ts-x in ts-0 transmit mode. selectable test patterns for line transmission. detection of framed and unframed pseudorandom and quasi-random test patterns. programmable squelch and idle codes. n system interface: autonomous transmit and receive system inter- faces. independent transmit and receive frame synchro- nization input signals. independent transmit and receive system inter- face clock. 2.048 mbits/s, 2.048 mhz concentration highway interface (chi) default mode. optional 4.096 mbits/s and 8.192 mbits/s data rates. optional 4.096 mhz, 8.192 mhz, and 16.384 mhz frequency system clock. programmable clock edge for latching frame syn- chronization signals. programmable clock edge for latching transmit and receive data. programmable bit and byte offset. programmable chi master mode for the genera- tion of the transmit chi fs from internal logic with timing derived from the receive line clock signal. n digital phase comparator for clock generation in the receive and transmit paths. facility data link features n hdlc or transparent mode. n automatic transmission of the esf performance report messages (prm). n detection of the esf prm. n detection of the ansi esf fdl bit-oriented codes. n 64-byte fifo in both transmit and receive directions. n programmable fifo full- and empty-level interrupt. n slc -96: fdl transmit and receive register access of d bits. user-programmable microprocessor inter- face n 33 mhz read and write access with no wait-states. n 12-bit address, 8-bit data interface. n programmable intel or motorola interface modes. n demultiplexed or multiplexed address and data bus. n directly addressable internal registers. n no clock required. preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 14 lucent technologies inc. lucent technologies inc. functional description 5-4512(f).cr.2 figure 1. T7630 block diagram (one of two channels) receive channel [12] microprocessor interface interrupt rdy_dtack wr _ds rd _r/w ale _as cs ad[7:0] a[11:0] tchick rtip_rpd[12] rring_rnd[12] rlck[12] cept: ts16) or (ds1: robbed-bit signaling unit receive transmit concentration highway interface phase detector channel digital receive receive facility data link monitor transparent framing) (hdlc or receive line interface unit receive framer unit (2 frames) elastic store receive ttip[12] tring[12] transmit framer unit phase detector channel digital transmit sysck[12] transmit facility data link monitor transparent framing) (hdlc or xmit framer tclk rchick channel [12] transmit receive concentration highway interface (2 frames) elastic store transmit transmit line interface unit cept: ts16) or (ds1: robbed-bit signaling unit transmit tchick[12] tchifs[12] tchidata[12] tchidatab[12] rfdl[12], rfdlck[12] rfrmck[12], rfrmdata[12], rfs[12], rssfs[12], div-rlck[12], div-tchick[12], tchick-epll[12] rchick[12] rchifs[12] rchidata[12] tfs[12], tssfs[12], div-pllck[12], div-rchick[12], pllck-epll[12] pllck[12] tfdl[12], tfdlck[12] rchdatab[12] mpmode mpmux (xliu) (rchi) (rliu) (tchi) rlck tnd[12], tcrcmfs[12] tpd[12], rcrcmfs[12] mpck tlck[12] lucent technologies inc. 15 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. functional description (continued) the lucent T7630 dual t1/e1 terminator (terminator- ii) provides two complete t1/e1 interfaces each con- sisting of a fully integrated, full-featured, short-haul line interface transceiver and a full-featured primary rate framer with an hdlc formatter for facility data link access. the T7630 provides glueless interconnection from a t1 or e1 analog line interface to devices inter- facing to its chi; for example, the t7270 time-slot interchanger or t7115a synchronous protocol data formatter. the line interface receiver performs clock and data recovery using a digital phase-locked loop, thereby avoiding false lock conditions that are common when recovering sparse data patterns with an analog imple- mentation. the receivers equalization circuit guaran- tees a high level of interference immunity. the receive line unit monitors the amplitude at the receive input for analog loss of signal (alos) detection and the pulse density of the receive signal for digital loss of signal (dlos) detection. the receive line unit may be pro- grammed to detect bipolar violations. the line interface unit may be optionally bypassed. it is recommended that the liu/framer interface be placed in dual-rail mode, which allows the framers error/event detector to detect and report code and bipolar violation (bpv) errors. the line interface units transmit equalization is done with low-impedance output drivers that provide shaped waveforms to the transformer, guaranteeing template conformance. the transmitter will interface to the digital cross connect (dsx) at lengths up to 655 feet for ds1 operation, and line impedances of 75 w or 120 w for cept-e1 operation. the transmit line unit monitors nonfunctional links due to faults at the primary of the transmit transformer and periods of no data transmis- sion. the line codes supported in the framer unit include ami, t1 b8zs, per-channel t1 zero code suppression and itu-cept hdb3. the T7630 supports t1 d4, t1dm, and slc -96 sf, esf; itu-cept-e1 basic frame; itu-cept-e1 time slot 0 multiframe; and time slot 16 multiframe formats. the receive framer monitors the following alarms: loss of receive clock, loss of frame, alarm indication signal (ais), remote frame alarms, and remote multiframe alarms. these alarms are detected as defined by the appropriate ansi, at&t, and itu standards. performance monitoring as specified by at&t, ansi , and itu is provided through counters monitoring bipo- lar violation, frame bit errors, crc errors, cept e bit = 0 conditions, cept sa6 codes, errored events, errored seconds, bursty errored seconds, severely errored sec- onds, and unavailable seconds. in-band loopback activation and deactivation codes can be transmitted to the line via the payload or the facility data link. in-band loopback activation and deac- tivation codes in the payload or the facility data link are detected. system, payload, and line loopbacks are programma- ble. the default system interface is a 2.048 mbits/s data and 2.048 mhz clock chi serial bus. this chi interface consists of independent transmit and receive paths. the chi interface can be reconfigured into several modes: a 2.048 mbits/s data interface and 4.096 mhz clock interface, a 4.096 mbits/s data interface and 4.096 mhz clock interface, a 4.096 mbits/s data inter- face and 8.192 mhz clock interface, a 8.192 mbits/s data interface and 8.192 mhz clock interface, and 8.192 mbits/s data interface and 16.384 mhz clock interface. the signaling formats supported are t1 per-channel robbed-bit signaling (rbs), channel-24 message-ori- ented signaling (mos), and itu-cept-e1 channel- associated signaling (cas). in the t1, rbs mode voice and data channels are programmable. the entire pay- load can be programmed into a data-only (no signaling channels) mode, i.e., transparent mode. signaling access can be through the on-chip signaling registers or the system chi port in the associated signaling mode. data and its associated signaling information can be accessed through the chi in either ds1 or cept-e1 modes. extraction and insertion of the facility data link in esf, t1dm, slc -96, or cept-e1 modes are provided through a four-port serial interface or through a micro- processor-accessed, 64-byte fifo either with hdlc formatting or transparently. in the T7630s slc -96 or cept-e1 frame formats, a facility data link (fdl) is pro- vided for fdl access. the bit-oriented esf data-link messages defined in ansi t1.403-1995 are monitored by the receive framers facility data link unit and are transmitted by the transmit framer fdl the receive framer includes a two-frame elastic store buffer for jitter attenuations that performs control slips and provides indication of slip directions. accessing internal registers is done via the demulti- plexed/multiplexed address and data bus microproces- sor interface using either the intel 80188 (or 80x88) interface protocol with independent read and write sig- nals or the motorola mc680x0 or m68360 interface protocol with address and data strobe signals. preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 16 lucent technologies inc. lucent technologies inc. functional description (continued) the T7630 is manufactured using low-power cmos technology and is packaged in an 144-pin thin quad flat pack (tqfp) with 20 mils lead pitch. 5-4513(f).c figure 2. T7630 block diagram: receive section (one of two channels) rtip_rpd rring_rnd rlck recovery data digital or transmit) (optional: attenuation jitter receive and monitor bpv decoder transmit concentration highway interface (rate adapter) tchifs (2 frames) receive elastic store buffer monitor receive slip internal system clock tchick C microprocessor access C concentration highway access C cept channel associated and common channel signaling C ds1 robbed-bit signaling (rbs) receive signaling extracter: rfdlck rfdl & signaling multiframe C cept: basic frame, crc-4 multiframe, C esf C sf: d4, slc -96, dds re-aligner, and sync generator: receive t1/e1 frame alignment monitor, C unavailable seconds C severely errored seconds C bursty errored seconds C errored seconds C errored events C bipolar violation errors receive performance monitor: C slips C alarm indication signal (ais) C cept remote multiframe alarm C remote frame alarm C digital loss of signal C analog loss of signal receive alarm monitor: ? message-oriented messages ? bit-oriented messages C ansi t1.403-1989 esf format: C dds access C slc -96 format and monitor: receive facility data link extracter rfrmck front end receive analog analog clock and line interface unit bypass rpd-liu, rnd-liu, rpde, rnde, rlcke rpd, rnd, rlck receive pattern monitor: C quasi-random: 2 20 C 1 C pseudorandom: 2 15 C 1 C ansi t1.403 bit-oriented and esf-fdl activate and deactivate line loopback codes C cept auxiliary pattern (cept = 01) C cept activate and deactivate loopback C cept sa6 codes C t1/e1 crc errors receive fdl hdlc extracter: C 64-byte receive fifo C transparent mode (no hdlc framing) C microprocessor access tchidata tchidatab framer rlck-liu codes test pattern detector C mark (allones) C qrss (quasi-random: 2 20 C 1) C 2 5 C 1 C 2 6 C 1 (53) C 2 9 C 1 (511) C 2 11 C 1 (2047) C 2 15 C 1 (pseudorandom) C 2 20 C 1 C 2 23 C 1 C 1:1 (alternating 10) lucent technologies inc. 17 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. functional description (continued) 5-4514(f).d figure 3. T7630 block diagram: transmit section (one of two channels) ttip tring transmit data monitor pulse equalizer and width controller all ones signal (ais) sysck ? 16 jitter (optional: receive) at t e n uat i o n transmit or bpv (optional) encoder tlck, tnd, tpd transmit crc generator: C esf C cept transmit t1/e1 frame formatter, and frame sync generator: C sf: d4, slc -96, dds; signaling C esf C cept: basic frame, crc-4 multiframe, & signaling multiframe C transparent framing superframe transmit facility data link C slc -96 format C dds access C ansi t1.403-1989 esf format: ? bit-oriented messages ? message-oriented messages transmit fdl hdlc inserter: C 64-byte transmit fifo C transparent mode C microprocessor access (no hdlc framing) inserter: tfdlck tfdl line format encoder (ami; b8zs; hdb3) tlck, tnd, tpd automatic and on-demand commands: C ais (line, system, fdl) C loopbacks C remote frame alarms (rfa) C cept e bit = 0 C cept ts16 ais C cept ts16 rpa transmit elastic store buffer (2 frames) receive concentration highway interface (rate adapter) rchick rchifs rchidata transmit alarm monitor: C loss of system biframe alignment C system alarm indication signal (ais) rchidatab transmit signaling inserter: C ds1 robbed-bit signaling (rbs) C cept channel associated and C concentration highway access C microprocessor access common-channel signaling loss of tlck test pattern generator C mark (all1s) C qrss C 2 5 C 1 C 2 6 C 1 (53) C 2 9 C 1 (511) C 2 11 C 1 (2047) C 2 15 C 1 C 2 20 C 1 C 2 23 C 1 C 1:1 (alternating 10) pllck preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 18 lucent technologies inc. lucent technologies inc. pin information the package type and pin assignment for the T7630 (terminator-ii) is illustrated in figure 4. 5-4712(f).cr.2 figure 4. pin assignment grnd nc rfrmck1 rlck1 tlck1 tnd1 tpd1 grnda1 nc rring_rnd1 rtip_rpd1 nc v dda1 grndx1 tring1 v dd x 1 ttip1 grndx1 grnds grndx2 ttip2 v dd x 2 tring2 grndx2 v dda2 nc rtip_rpd2 rring_rnd2 nc grnda2 tpd2 tnd2 tlck2 rlck2 nc grnd 36 37 v dd rfrmck2 rfrmdata2 rfs2 rssfs2 rcrcmfs2 rfdlck2 rfdl2 tchick2 tchifs2 tchidata2 tcasdata2 div-rlck2 div-tchick2 tchick-epll2 tfs2 tssfs2 tcrcmfs2 tfdlck2 tfdl2 rchick2 rchifs2 rchidata2 rcasdata2 pllck2 div-pllck2 pllck-epll2 sysck2 lorlck2 lopllck2 ds1/cept 2 framer 2 3-state 2 reset 2 v dd 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 v dd wr _ds trst tms tck tdi tdo mpck rdy_dtack interrupt a11 a10 a9 a8 a7 a6 a5 a4 a2 a3 a1 a0 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 ale _as cs mpmux rd _r/w mpmode grnd 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 v dd rfrmdata1 rfs1 rssfs1 rcrcmfs1 rfdlck1 rfdl1 tchick1 tchifs1 tchidata1 tcasdata1 div-rlck1 div-tchick1 tchick-epll1 tfs1 tssfs1 tcrcmfs1 tfdlck1 tfdl1 rchick1 rchifs1 rchidata1 rcasdata1 pllck1 div-pllck1 div-rchick1 pllck-epll1 sysck1 lorlck1 lopllck1 ds1/cept1 framer 1 3-state 1 reset 1 second grnd div-rchick2 lucent technologies inc. 19 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. pin information (continued) table 1 and table 2 show the list of T7630 pins and a functional description for each. table 1. pin descriptions-channel 1 and channel 2 * i u indicates an internal pull-up. ? after reset is deasserted, the channel is in the default framing mode, as a function of the ds1/cept pin. ? asserting this pin low will initially force rdy to a low state. pin symbol type * description ch1 ch2 1, 36, 73, 109 grnd p digital ground reference. 2 38 lofrmrlck o loss of framer receive line clock. this pin is asserted high (1) when the framer internal receive line clock does not toggle for a 250 m s interval. once asserted, this signal is deasserted on the first edge of the framer internal receive line clock. terminator mode: (framer , pin 41/141 = 1) lofrmrlck is asserted high when sysck clock, pin 3/35, is absent. framer mode: (framer , pin 41/141 = 0) lofrmrlck is asserted high when rlck clock, pin 47/135, is absent. 335 sysck i u liu system clock. the clock signal used for clock and data recovery and jit- ter attenuation. this clock must be ungapped and free of jitter. for cksel = 1, a 16x clock (for ds1, sysck = 24.704 mhz 100 ppm and for cept, sysck = 32.768 mhz 100 ppm). for cksel = 0, a 1x clock (for ds1, sysck = 1.544 mhz 100 ppm and for cept, sysck = 2.048 mhz 100 ppm). 434pllck-epll o error phase-lock loop signal. the error signal proportional to the phase difference between div-pllck and div-rchick as detected by the internal pll circuitry (refer to the phase-lock loop circuit section). 5 33 div-rchick o divided-down rchi clock. 32 khz or 8 khz clock signal derived from the rchick input signal. 632 div-pllck o divided-down pllck clock. 32 khz or 8 khz clock signal derived from the pllck input signal. 731 pllck i transmit framer phase-locked line interface clock. clock signal used to time the transmit framer. this signal must be phase-locked to rchick clock signal and be ungapped and free of jitter. for frm_pr45, bit 0 (hflf) = 0, in ds1 pllck = 1.544 mhz and in cept pllck = 2.048 mhz. for frm_pr45, bit 0 (hflf) = 1 in ds1 pllck = 6.176 mhz and in cept pllck = 8.192 mhz. 8 30 grnd a p analog ground reference. 9, 12, 19, 26, 29 nc no connection. 10 28 rring_rnd i receive bipolar ring. negative bipolar input data from the receive analog line isolation transformer. receive negative rail data. valid when the framer pin is strapped to 0 v. nonreturn-to-zero (nrz) serial data latched by the rising edge of rlck. data rates: ds1-1.544 mbits/s; cept-2.048 mbits/s. in the single-rail mode, when rnd = 1 the receive bipolar violation counter increments once for each rising edge of rlck. preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 20 lucent technologies inc. lucent technologies inc. pin information (continued) table 1. pin descriptions-channel 1 and channel 2 (continued) * i u indicates an internal pull-up. ? after reset is deasserted, the channel is in the default framing mode, as a function of the ds1/cept pin. ? asserting this pin low will initially force rdy to a low state. pin symbol type * description ch1 ch2 11 27 rtip_rpd i receive bipolar tip. positive bipolar input data from the receive analog line isolation transformer. receive positive rail data. valid when the framer pin is strapped to 0 v. nrz serial data latched by the rising edge of rlck. data rates: ds1-1.544 mbits/s; cept-2.048 mbits/s. optional single-rail nrz receive data latched by the rising edge of rlck. 13 25 v dda p analog 5 v power supply. 5 v 5%. 14, 18 20, 24 grndx p transmit line driver ground reference. 15 23 tring o transmit bipolar ring. negative bipolar output data to the transmit analog isolation transformer. 16 22 v dd xp transmit line driver 5 v power supply. 5 v 5%. 17 21 ttip o transmit bipolar tip. positive bipolar output data to the transmit analog isolation transformer. 37, 72, 108, 144 v dd p 5 v power supply. 5 v 5%. 143 39 lopllck o loss of pllck clock. this pin is asserted high when the pllck clock does not toggle for a 250 s interval. this pin is deasserted 250 s after pllck clock restarts toggling. 142 40 ds1/cept i u ds1/cept . strap to v dd to enable defaults for ds1 operation. strap to v ss to enable defaults for cept operation. 141 41 framer i u framer mode. strap to v dd to enable integrated liu and framer operation. strap to v ss to bypass the liu section; the receive framer is sourced directly from the rpd, rnd, and rlck pins while the tpd, tnd, and tlck pins are driven by the transmit framer. 140 42 3-state i u 3-state (active-low). asserting this pin low forces the channel outputs into a high-impedance state. asserting both 3-state pins low forces all outputs into a high-impedance state. 139 43 reset ? i u reset (active-low). asserting this pin low resets the channel. asserting both reset pins low resets the entire device including the global registers. 138 44 tpd o transmit line interface positive-rail data. this signal is the transmit framer positive nrz output data. data changes on the rising edge of tlck. in the single-rail mode, tpd = transmit framer data. lucent technologies inc. 21 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. pin information (continued) table 1. pin descriptions-channel 1 and channel 2 (continued) * i u indicates an internal pull-up. ? after reset is deasserted, the channel is in the default framing mode, as a function of the ds1/cept pin. ? asserting this pin low will initially force rdy to a low state. pin symbol type * description ch1 ch2 137 45 tnd o transmit line interface negative-rail data. this signal is the transmit framer negative nrz output data. data changes on the rising edge of tlck. in the single-rail mode, tnd = 0. 136 46 tlck o transmit framer line interface clock. optional 1.544 mhz ds1 or 2.048 mhz output signal from the transmit framer. tnd and tpd data changes on the rising edge of tlck. 135 47 rlck i receive framer line interface clock. valid when the framer pin is strapped to 0 v. this is the 1.544 mhz ds1 or 2.048 mhz input clock signal used by the receive framer to latch rpd and rnd data. 134 49 rfrmck o receive framer clock. output receive framer clock signal used to clock out the receive framer output signals. in normal operation, this is the recovered receive line clock signal. 133 48 cksel i u liu system clock mode. this pin selects either a 16x rate clock for sysck (cksel = 1) or a primary line rate clock for sysck (cksel = 0). 132 50 rfrmdata o receive framer data. this signal is the decoded data input to the receive elastic store. during loss of frame alignment, this signal is forced to 1. 131 51 rfs o receive frame sync. this active-high signal is the 8 khz frame synchroni- zation pulse generated by the receive framer. 130 52 rssfs o receive framer signaling superframe sync. this active-high signal is the cept signaling superframe (multiframe) synchronization pulse in the receive framer. 129 53 rcrcmfs o receive framer crc-4 multiframe sync. this active-high signal is the cept crc-4 multiframe synchronization pulse in the receive framer. 128 54 rfdlck o receive facility data link clock. in ds1-dds with data link access, this is an 8 khz clock signal. otherwise, this is a 4 khz clock signal. the receive data link bit changes on the falling edge of rfdlck. 127 55 rfdl o receive facility data link. serial output facility data link bit stream extracted from the receive line data stream by the receive framer. in ds1- dds with data link access, this is an 8 kbits/s signal; otherwise, 4 kbits/s. in the cept frame format, rfdl can be programmed to one of the sa bits of the not fas frame ts0. during loss of frame alignment, this sig- nal is 1. 126 56 tchick i transmitrchi clock. 2.048 mhz, 4.096 mhz, 8.192 mhz, or 16.384 mhz. this clock must be free of jitter. 125 57 tchifs i/o transmit chi frame sync. transmit chi 8 khz input frame synchronization pulse phase-locked to tchick. in the chi master mode, the transmit chi generates the 8 khz frame sync to control the chi. preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 22 lucent technologies inc. lucent technologies inc. pin information (continued) table 1. pin descriptions-channel 1 and channel 2 (continued) * i u indicates an internal pull-up. ? after reset is deasserted, the channel is in the default framing mode, as a function of the ds1/cept pin. ? asserting this pin low will initially force rdy to a low state. pin symbol type * description ch1 ch2 124 58 tchidata o transmit chi data. serial output system data at 2.048 mbits/s, 4.096 mbits/s, or 8.192 mbits/s. this port is forced into a high-impedance state for all inactive time slots. 123 59 tchidatab o transmit chi data b. serial output system data at 2.048 mbits/s, 4.096 mbits/s, or 8.192 mbits/s. this port is forced into a high-impedance state for all inactive time slots. 122 60 div-rlck o divided-down receive line clock. 8 khz clock signal derived from the recovered receive line interface unit clock or the rlck input signal. 121 61 div-tchick o divided-down chi clock. 8 khz clock signal derived from the transmit chi clock input signal. 120 62 tchick-epll o error phase-lock loop signal. the error signal proportional to the phase difference between div-tchick and div-rlck as detected from the internal pll circuitry (refer to the phase-lock loop circuit section. 119 63 tfs o transmit framer frame sync. this signal is the 8 khz frame synchroniza- tion pulse in the transmit framer. this signal is active-high. 118 64 tssfs o transmit framer signaling superframe sync. this signal is the cept signaling superframe (multiframe) synchronization pulse in the transmit framer. this signal is active-high. 117 65 tcrcmfs o transmit framer crc-4 multiframe sync. this signal is the cept crc-4 submultiframe synchronization pulse in the transmit framer. this signal is active-high. 116 66 tfdlck o transmit facility data link clock. in ds1-dds with data link access, this is an 8 khz clock signal; otherwise, 4 khz. the transmit frame latches data link bits on the falling edge of tfdlck. 115 67 tfdl i transmit facility data link. optional serial input facility data link bit stream inserted into the transmit line data stream by the transmit framer. in ds1- dds with data link access, this is an 8 kbits/s signal; otherwise, 4 kbits/s. in the cept frame format, tfdl can be programmed to one of the sa bits of the not-fas frame time slot 0. 114 68 rchick i receive chi clock. 2.048 mhz, 4.096 mhz, 8.192 mhz, or 16.384 mhz. this clock must be free of jitter. 113 69 rchifs i receive chi frame sync. receive chi 8 khz frame synchronization pulse phase-locked to rchick. 112 70 rchidata i receive chi data. serial input system data at 2.048 mbits/s, 4.096 mbits/s, or 8.192 mbits/s. 111 71 rchidatab i receive chi data b. serial input system data at 2.048 mbits/s, 4.096 mbits/s, or 8.192 mbits/s. lucent technologies inc. 23 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. pin information (continued) table 2. pin descriptions-global * i u indicates an internal pull-up. i d indicates an internal pull-down. ? after reset is deasserted, the channel is in the default framing mode, as a function of the ds1/cept pin. ? asserting this pin low will initially force rdy to a low state. pin symbol type * description 74 mpmode i u mpmode. strap to ground to enable the motorola 68360 microprocessor protocol (mode1 or mode2). strapped to v dd to enable the intel 80x86/88 microprocessor protocol (mode3 or mode4). 75 rd _r/w i read (active-low). in the intel interface mode, the T7630 drives the data bus with the contents of the addressed register while rd is low. read/write . in the motorola interface mode, this signal is asserted high for read accesses; this pin is asserted low for write accesses. 76 mpmux i u mpmux. strap to v ss to enable the demultiplexed address and data bus mode. strap to v dd to enable the multiplexed address and data bus mode. 77 c s ? i chip select (active-low). in the intel interface mode, this pin must be asserted low to initiate a read or write access and kept low for the duration of the access; asserting cs low forces rdy out of its high-impedance state into a 0 state. 78 ale _a s i address latch enable/address strobe. in the address/data bus multiplex mode of the microprocessor, when this signal transitions from high to low, the state of the address bus is latched into internal address registers. in the demultiplexed address mode, the address is transparent through the T7630 and is latched on the rising edge of the ale _as signal. alternatively, if ale _as is not connected to the micropressor or other driver, it must be con- nected to ground. 7986 ad0ad7 i/o microprocessor address_data bus. multiplexed address and bidirectional data bus used for read and write accesses. high-impedance output. 8798 a0a11 i microprocessor address bus. address bus used to access the internal reg- isters. 99 interrupt o interrupt. interrupt is asserted high indicating an internal interrupt condi- tion/event has been generated. otherwise, interrupt is 0. interrupt events/conditions are maskable through the control registers. interrupt asser- tion may be inverted (active-low) by setting register greg 4 bit 6 = 1. this output may not be wire or connected to any other logic output. preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 24 lucent technologies inc. lucent technologies inc. pin information (continued) table 2. pin descriptions-global (continued) * i u indicates an internal pull-up. ? after reset is deasserted, the channel is in the default framing mode, as a function of the ds1/cept pin. pin symbol type * description 100 rdy_dtack o ready. in the intel interface mode, this pin is asserted high to indicate the completion of a read or write access; this pin is forced into a high-impedance state while cs is high. data transfer acknowledge (active-low). in the motorola interface mode, dtack is asserted low to indicate the completion of a read or write access; dtack is 1 otherwise. 101 mpck i u microprocessor clock. microprocessor clock used in the intel mode to generate the ready signal. 102 jtagtdo o jtag data output. serial output data sampled on the falling edge of tck from the boundary-scan test circuitry. 103 jtagtdi i u jtag data input. serial input data sampled on the rising edge of tck for the boundary-scan test circuitry. 104 jtagtck i u jtag clock input. tck provides the clock for the boundary-scan test logic. 105 jtagtms i u jtag mode select (active-high). the signal values received at tms are sampled on the rising edge of tck and decoded by the boundary-scan tap controller to control boundary-scan test opera- tions. 106 jtagtrst i d jtag reset input (active-low). assert this pin low to asynchro- nously initialize/reset the boundary-scan test logic. 107 wr _ds i write (active-low). in the intel mode, the value present on the data bus is latched into the addressed register on the positive edge of the signal applied to wr . data strobe (active-low). in the motorola mode, when as is low and r/w is low (write), the value present on the data bus is latched into the addressed register on the positive edge of the signal applied to ds ; when as is low and r/w is high (read), the T7630 drives the data bus with the contents of the addressed register while ds is low. 110 second o second pulse. a one second timer with an active-high pulse. the duration of the pulse is one rlck cycle. the received line clock of framer1 (rlck1) is the default clock source for the internal sec- ond pulse timer. when lofrmclk1 is active, the received line clock of framer2 is used as the clock signal source for the inter- nal second pulse timer. the second pulse is used for performance monitoring. pin information (continued) table 2. pin descriptions-global (continued) * i u indicates an internal pull-up. i d indicates an internal pull-down. ? after reset is deasserted, the channel is in the default framing mode, as a function of the ds1/cept pin. ? asserting this pin low will initially force rdy to a low state. pin symbol type * description 100 rdy_dtack o ready. in the intel interface mode, this pin is asserted high to indicate the completion of a read or write access; this pin is forced into a high-impedance state while cs is high. data transfer acknowledge (active-low). in the motorola interface mode, dtack is asserted low to indicate the completion of a read or write access; dtack is 1 otherwise. 101 mpck i u microprocessor clock. microprocessor clock used in the intel mode to generate the ready signal. 102 jtagtdo o jtag data output. serial output data sampled on the falling edge of tck from the boundary-scan test circuitry. 103 jtagtdi i u jtag data input. serial input data sampled on the rising edge of tck for the boundary-scan test circuitry. 104 jtagtck i u jtag clock input. tck provides the clock for the boundary-scan test logic. 105 jtagtms i u jtag mode select (active-high). the signal values received at tms are sampled on the rising edge of tck and decoded by the boundary-scan tap controller to control boundary-scan test opera- tions. 106 jtagtrst i d jtag reset input (active-low). assert this pin low to asynchro- nously initialize/reset the boundary-scan test logic. 107 wr _ds i write (active-low). in the intel mode, the value present on the data bus is latched into the addressed register on the positive edge of the signal applied to wr . data strobe (active-low). in the motorola mode, when as is low and r/w is low (write), the value present on the data bus is latched into the addressed register on the positive edge of the signal applied to ds ; when as is low and r/w is high (read), the T7630 drives the data bus with the contents of the addressed register while ds is low. 110 second o second pulse. a one second timer with an active-high pulse. the duration of the pulse is one rlck cycle. the received line clock of framer1 (rlck1) is the default clock source for the internal sec- ond pulse timer. when lofrmclk1 is active, the received line clock of framer2 is used as the clock signal source for the inter- nal second pulse timer. the second pulse is used for performance monitoring. lucent technologies inc. 25 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) lucent technologies inc. line interface unit: block diagram the T7630 liu diagram is shown in figure 5. only a single transceiver is shown here for illustration purposes. 5-4556(f).g figure 5. block diagram of line interface unit: single channel to receive from transmit framer rtip rring flloop (no liu ais) equalizer slicers clock and data recovery rdlos rnd_bpv rpd rlck decoder dlloop rloop tlck-liu tnd-liu jitter (receive path) tpd-liu flloop (during liu ais) pulse- width controller tdm lotc pulse equalizer transmit driver ttip tring sysck loss of sysck monitor divide by 16 alarm signal (ais) encoder framer ralos indication at t e n uato r jitter (transmit path) at t e n uato r (clock) (data) loss of tlck line length indicator (uncommitted feature) lbo 0.0 db 7.5 db 15.0 db 22.5 db line interface unit: receive data recovery the receive line-interface unit (rliu) transmission for- mat is bipolar alternate mark inversion (ami). the rliu accepts input data with a data rate tolerance of 130 ppm (ds1) or 80 ppm (e1). the rliu first restores the incoming data and detects alos. subse- quent processing is optional and depends on the pro- grammable liu configuration established within the microprocessor interface registers. the rliu utilizes an adaptive equalizer to operate on line length with typ- ically up to 3615 db of loss at 772 khz (t1/ds1) or 4313 db loss at 1.024 mhz (e1). the signal is then peak-detected and sliced to produce digital representa- tions of the data. selectable dlos, jitter attenuation, and data decoding are performed. the clock is recovered by a digital phase-locked loop that uses sysck as a reference to lock to the data rate component. because the reference clock is a multiple of the received data rate, the internal rlck (rlck- liu) output will always be a valid ds1/cept clock that eliminates false lock conditions. during periods with no receive input signal from the line, the free-run fre- quency of rlck-liu is defined to be either sysck/16 or sysck depending on the state of cksel . rlck- liu is always active with a duty cycle centered at 50%, deviating by no more than 5%. valid data is recovered within the first few bit periods after the application of sysck. preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 26 lucent technologies inc. lucent technologies inc. line interface unit: receive (continued) jitter accommodation and jitter transfer without the jitter attenuator the rliu is designed to accommodate large amounts of input jitter. the rlius jitter performance exceeds the requirements shown in the rliu specification table 5 and table 6. typical receiver performance with- out the jitter attenuator in the path is shown in figures 69. typical receiver performance with the jit- ter attenuator is given in figures 1215. jitter transfer is independent of input ones density on the line inter- face. receive line interface configuration modes zero substitution decoding (code) when single-rail operation is selected with dual = 0 (register liu_reg3, bit 3), the liu b8zs/hdb3 zero substitution decoding can be selected via the code bit (register liu_reg3, bit 2). if code = 1, the b8zs/ hdb3 decoding function is enabled in the receive path. decoded receive data appears at the internal liu-to- framer rpd interface (rpd-liu). code violations, including bpvs, appear at the internal liu-to-framer rnd_bpv interface (rnd-liu). if code = 0, the receive data is passed unaltered to rpd-liu, and all bipolar violations (such as two consecutive ones if the same polarity) appear at rnd-liu. the default configu- ration is single-rail, dual = 0, with the decoding active, code = 1. if dual = 0, the receive framer must be programmed to the single-rail mode and the receive framers internal liu-to-framer rpd input will be the receive data port. if dual = 0, then the receive framers bipolar violation count will increment by one whenever the internal liu- to-framer rnd_bpv signal is one. the bipolar violation count is incremented on the rising edge of the receive framers rlck clock signal. receive line interface unit (rliu) alarms analog loss of signal (alos) alarm . an analog sig- nal detector monitors the receive signal amplitude and reports its status in the alos alarm bit alos (register liu_reg0, bit 0). alos is indicated (alos = 1) if the amplitude at the rring and rtip inputs drops below a voltage approximately 18 db below the nominal signal amplitude. the alos alarm condition will clear when the receive signal amplitude returns to a level greater than 14 db below normal. the alos alarm status bit will latch the alarm and remain set until being cleared by a read (clear on read). upon the transition from alos = 0 to alos = 1, a microprocessor interrupt will be generated if the alos interrupt enable bit alosie (register liu_reg1, bit 0) is set. the reset default is alosie = 0. the alos circuitry provides 4 db of hysteresis to pre- vent alarm chattering. the time required to detect alos is selectable. when altimer = 0 (register liu_reg4, bit 0), alos is declared between 1 ms and 2.6 ms after losing signal as required by i.431(3/93) and ets-300-233 (5/94). if altimer = 1, alos is declared between 10-bit and 255-bit symbol periods after losing signal as required by g.775 (11/95). the timing is derived from the sysck clock. the detection time is independent of signal amplitude before the loss condition occurs. normally, altimer = 1 would be used only in e1 mode since no t1/ds1 standards require this mode. in t1/ds1 mode, this bit should nor- mally be zero. the reset default is altimer = 0. the behavior of the receiver rliu outputs under alos conditions is dependent on the loss shutdown (lossd) control bit (register liu_reg3, bit 4) in conjunction with the receive alarm indication select (rcvais) con- trol bit (register liu_reg4, bit 1) as described in the loss shutdown (lossd) and receiver ais (rcvais) section on page 27. when operating on long-haul loops, the receive input signal will routinely be well below the 20 db alos level. therefore, when the transmit equalization is programmed to any of the long- haul settings shown in table 8, the alos function is completely disabled. digital loss of signal (dlos) alarm. a (dlos) detector guarantees the received signal quality as defined in the appropriate ansi , bellcore , and itu standards. the dlos alarm is reported in the rliu alarm status register (register liu_reg0, bit 1). for ds1 operation, digital loss of signal (dlos = 1) is indi- cated if 100 or more consecutive zeros occur in the receive data stream. the dlos condition is deacti- vated when the average ones density of at least 12.5% is received in 100 contiguous pulse positions. the dlos alarm status bit will latch the alarm and remain set until being cleared by a read (clear on read). the losstd control bit (register liu_reg2, bit 2) selects the conformance protocols for the dlos alarm indica- tion per table 3. setting losstd = 1 adds an addi- tional constraint that there are less than 15 consecutive zeros in the ds1 data stream before dlos is deacti- vated. the reset default is losstd = 0. lucent technologies inc. 27 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. line interface unit: receive (continued) for e1 operation, dlos is indicated when 255 or more consecutive zeros occur in the receive data stream. the dlos indication is deactivated when the average ones density of at least 12.5% is received in 255 contig- uous pulse positions. losstd has no effect in e1 mode. upon the transition from dlos = 0 to dlos = 1, a microprocessor interrupt will be generated if the dlos interrupt enable bit dlosie (register liu_reg1, bit 1) is set. the reset default is dlosie = 0. the dlos alarm may occur when flloop is activated (see line interface unit: loopbacks) due to the abrupt change in signal level at the receiver input. setting the flloop alarm prevention pflalm = 1 (register liu_reg 4, bit 2) prevents the dlos alarm from occurring when flloop is activated by quickly reset- ting the receivers internal peak detector. it will not pre- vent the dlos alarm during the flloop period but only avoids the alarm created by the signal amplitude transient. the reset default is pflalm = 0. table 3. dlos standard select loss shutdown (lossd) and receiver ais (rcvais). the loss shutdown (lossd) control bit (reg- ister liu_reg3, bit 4) acts in conjunction with the receive alarm indication select (rcvais) control bit (register liu_reg4, bit 1) to place the digital rliu sig- nals (rpd-liu, rnd-liu, rlck-liu) in a predeter- losstd ds1 mode cept mode 0 t1m1.3/93-005, itu-t g.775 itu-t g.775 1 tr-tsy-000009 itu-t g.775 mined state when a dlos or alos alarm occurs. if lossd = 0 and rcvais = 0, the rnd-liu, rpd- liu, and rlck-liu signals will be unaffected by the dlos alarm condition. however, when an alos alarm condition is indicated in the liu alarm status register (register liu_reg0, bit 0), the rpd-liu and rnd-liu signals are forced to 0 state and the rlck-liu free runs (at the intsysck/16 frequency). if lossd = 1, rcvais = 0, and a dlos alarm condi- tion is indicated in the liu alarm status register (regis- ter liu_reg0, bit 1) or an alos alarm condition is indicated, the rpd-liu and rnd-liu signals are forced to the inactive (dependent on alm) and the rlck-liu free runs (at the intsysck/16 frequency). if lossd = 0, rcvais = 1, and a dlos or an alos alarm condition is indicated in the liu alarm status reg- ister (register liu_reg0, bits 0 or 1), the rpd-liu and rnd-liu signals will present an alarm indication signal (ais, all ones) based on the free-running intsysck/ 16 frequency. if lossd = 1, rcvais = 1, and a dlos or an alos alarm condition is indicated in liu alarm status register (register liu_reg0, bits 0 or 1), the rpd-liu and rnd-liu signals are forced to inactive (dependent on alm) and the rlck-liu free runs at the intsysck/ 16 frequency. the rnd-liu, rpd-liu, and rlck-liu signals will be remain unaffected if any loopback (flloop, rloop, dlloop) is activated independent of lossd and rcvais settings. the default reset state is lossd = 0 and rcvais = 0. the lossd and rcvais behavior is summarized in table 4. table 4. lossd and rcvais control configurations (not valid during loopback modes) liu receiver bpv alarm. the receiver liu bpv alarm is used only in the single-rail mode. when b8zs(ds1)/ hdb3(e1) coding is not used (i.e., code = 0), any violations in the receive data (such as two or more consecutive ones on a rail) are indicated on the rnd-liu output. when b8zs(ds1)/hdb3(e1) coding is used (i.e., code = 1), the hdb3/b8zs code violations, as defined in the appropriate standards, are reflected on the rnd-liu output. lossd rcvais alarm rpd/rnd rlck 0 0 alos inactive (1/0 dependent on alm) free runs 0 0 dlos normal data recovered clock 1 0 alos inactive (1/0 dependent on alm) free runs 1 0 dlos inactive (1/0 dependent on alm) free runs 0 1 alos ais (all ones) free runs 0 1 dlos ais (all ones) free runs 1 1 alos inactive (1/0 dependent on alm) free runs 1 1 dlos inactive (1/0 dependent on alm) free runs preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 28 lucent technologies inc. lucent technologies inc. line interface unit: receive (continued) during t1/ds1 operation, the liu receiver will perform as specified in table 5. table 5. t1/ds1 liu receiver specifications 1. below the nominal pulse amplitude of 3.0 v with the line interface circuitry specified in the line interface unit: line inte rface networks section. 2. cable loss at 772 khz. 3. using lucent transformer 2795b and components listed in table 14. parameter min typ max unit spec analog loss of signal: threshold to assert threshold to clear hysteresis time to assert (altimer = 0) 23 17.5 1.0 18 14 4 16.5 12.5 2.6 db 1 db 1 db ms i.431 i.431 receiver sensitivity 2 11 15 db jitter transfer: 3 db bandwidth peaking 3.84 0.1 khz db figure 7 figure 13 generated jitter 0.04 0.05 uip-p tr-tsy-000499, itu-t g.824 jitter accommodation figure 6 figure 12 return loss: 3 51 khz to 102 khz 102 khz to 1.544 mhz 1.544 mhz to 2.316 mhz 14 20 16 db db db digital loss of signal: itu-t g.775, t1m1.3/93-005 tr-try-000009 itu-t g.775, t1m1.3/ 93-005 flag asserted when consecutive bit positions contain 100 zeros flag deasserted when data density is and 12.5 %ones maximum consecutive zeros are 15 99 zeros zeros lucent technologies inc. 29 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. line interface unit: receive (continued) during e1 operation, the liu receiver will perform as specified in table 6. table 6. cept liu receiver specifications 1. below the nominal pulse amplitude of 3.0 v for 120 w and 2.37 v for 75 w applications with the line circuitry specified in the line interface unit: line interface networks section. 2. cable loss at 1.024 mhz. 3. amount of cable loss for which the receiver will operate error-free in the presence of a C18 db interference signal summing with the intended signal source. 4. using lucent transformer 2795d or 2795c and components listed in table 14. parameter min typ max unit specification analog loss of signal: threshold to assert threshold to clear hysteresis time to assert (altimer = 0) time to assert (altimer = 1) 23 17.5 1.0 10 18 14 4 16.5 12.5 2.6 255 db 1 db 1 db ms ui i.431, etsi 300 233 i.431, etsi 300 233 g.775 receiver sensitivity 2 11 13.5 db interference immunity: 3 9 12 db itu-t g.703 jitter transfer: 3 db bandwidth, single-pole roll off peaking 5.1 0.5 khz db figure 9 figure 15 generated jitter 0.04 0.05 uip-p itu-t g.823, i.431 jitter accommodation figure 8 figure 14 return loss: 4 51 khz to 102 khz 102 khz to 2.048 mhz 2.048 mhz to 3.072 mhz 14 20 16 db db db itu-t g.703 digital loss of signal: itu-t g.775 flag asserted when consecutive bit positions contain 255 zeros flag deasserted when data density is (losstd = 1) 12.5 %ones preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 30 lucent technologies inc. lucent technologies inc. line interface unit: receive (continued) 5-5260(f) figure 6. t1/ds1 receiver jitter accommodation without jitter attenuator 5-5261(f) figure 7. t1/ds1 receiver jitter transfer without jitter attenuator 0.1 ui 1.0 ui 10 ui 100 ui 10 100 1k 10k 1 28 ui frequency (hz) 100k ty p i c a l (subject to device characterization) (non-sonet cat ii interfaces) gr-499-core i.431(ds1), g.824(ds1) tr-tsy-000009 (ds1, muxes) gr-499/1244-core (cat i interfaces) t1.408/i.431(ds1)/g.824(ds1) 60 40 20 0 1 10 100 1k 10 k 50 30 10 100 k frequency (hz) jitter out/jitter in (db) ty p i c a l (subject to device characterization) gr-499-core (non-sonet cat ii to cat ii) lucent technologies inc. 31 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. line interface unit: receive (continued) 5-5262(f)r.9 figure 8. cept/e1 receiver jitter accommodation without jitter attenuator 5-5263(f) figure 9. cept/e1 receiver jitter transfer without jitter attenuator 0.1 ui 1.0 ui 10 ui 100 ui 10 100 1k 10k 1 37 ui frequency (hz) g.823 100k typical (subject to device characterization) g.823,ets-300-011a1 i.431(cept)/ets-300-011 i.431(cept)/ets-300-011 frequency (h z ) jitter out/jitter in (db) 60 40 20 0 1 10 100 1k 10k 50 30 10 100k typical (subject to device characterization) g.735-9 without jitter reducer 32 32 lucent technologies inc. preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) october 2000 lucent technologies inc. line interface unit: transmit output pulse generation the line interface transmitter accepts a line rate clock and nrz data in single-rail mode (dual = 0) or posi- tive and negative nrz data in dual-rail mode (dual = 1) from the transmit framer unit or, optionally, the sys- tem interface. the line interface transmitter converts this data to a balanced bipolar signal (ami format) with optional b8zs(ds1)/hdb3(e1) encoding and optional jitter attenuation. low-impedance output drivers pro- duce the line transmit pulses. positive ones are output as positive pulses on ttip, and negative ones are out- put as positive pulses on tring. binary zeros are con- verted to null pulses. in dsx-1 applications, transmit pulse shaping is con- trolled by the on-chip pulse-width controller and pulse equalizer. the pulse-width controller produces high- speed timing signals to accurately control the transmit pulse widths. this eliminates the need for a tightly con- trolled transmit clock duty cycle that is usually required in discrete implementations. the pulse equalizer con- trols the amplitudes and shapes of the pulses. different pulse equalizations are selected through settings of eq2, eq1, and eq0 bits (register liu_reg6, bits 0 to 2) as described in table 7, transmit line interface short-haul equalizer/rate control below. the reset default state of the equalization bits eq2, eq1, and eq0 can be predetermined by setting the ds1_cept pin. the default transmit equalization is eq2, eq1, and eq0 = 000 (0 db t1/ds1) when ds1_cept = 1; eq2, eq1, and eq0 = 110 (cept 120 w /75 w ) when ds1_cept = 0. this feature aids in transmitting ais at the correct rate upon completion of hardware reset; see liu transmitter alarm indication signal generator (xlais) on table 33. table 7. transmit line interface short-haul equalizer/rate control * in ds1 mode, the distance to the dsx for 22-gauge pic (abam) cable is specified. use the maximum cable loss figures for other cable types. in cept mode, equalization is specified for coaxial or twisted-pair cable. ? reset default state is eq2, eq1, and eq0 = 000 when pin ds1_cept = 1 and eq2, eq1, and eq0 = 110 when pin ds1_cept = 0. ? loss measured at 772 khz. in 75 w applications, option 1 is recommended over option 2 for lower liu power dissipation. option 2 allows for the use of the same t rans- former as in cept 120 w applications (see line interface unit: line circuitry section). short-haul applications eq2 eq1 eq0 service clock rate transmitter equalization *? maximum cable loss to dsx ? feet meters db 0 0 0 dsx-1 1.544 mhz 0 to 131 0 to 40 0.6 0 0 1 131 to 262 40 to 80 1.2 0 1 0 262 to 393 80 to 120 1.8 0 1 1 393 to 524 120 to 160 2.4 1 0 0 524 to 655 160 to 200 3.0 101cept 2.048 mhz 75 w (option 2) 1 1 0 120 w or 75 w (option 1) 111 not used lucent technologies inc. 33 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. line interface unit: transmit (continued) liu transmitter configuration modes liu transmitter zero substitution encoding (code) liu transmitter zero substitution (b8zs/hdb3) encod- ing can be activated only in the single-rail (dual = 0) system/framer interface mode. it is activated by setting code = 1 (register liu_reg3, bit 2). data transmitted from the framer interface on tpd-liu will be b8zs/ hdb3 encoded before appearing on ttip and tring at the line interface. liu transmitter alarm indication signal generator (xlais) when the transmit alarm indication signal control is set (xlais = 1) for a given channel (see register liu_reg5, bit 1), a continuous stream of bipolar ones is transmitted to the line interface. the internal liu to framer tpd interface (tpd) and internal liu to framer tnd interface (tnd) signals are ignored during this mode. the xlais control is ignored when a remote loopback (rloop) is selected using loopback control bits loopa and loopb (register liu_reg5, bits 2 to 3). the clock source used for the alarm indication sig- nal is tlck if present or intsysck if tlck is not present. the clock tolerance must meet the nominal transmission specifications of 1.544 mhz 32 ppm for ds1 (t1) or 2.048 mhz 50 ppm cept (e1). the xlais bit is defaulted to 1 on hardware reset allowing the transmitter to send ais as soon as clocks are available, without needing to write the liu regis- ters * . because the transmit equalization bits are needed to determine the correct system rate (ds1/e1), the reset default state of the equalization bits eq2, eq1, eq0 (register liu_reg6, bits 02) can be pre- determined by setting the ds1_cept pin (see table 7). the default transmit equalization is eq2, eq1, and eq0 = 000 (0 db t1/ds1) when ds1_cept = 1, and eq2, eq1, and eq0 = 110 (cept 120 w /75 w ) when ds1_cept = 0. the transmit equalization bits can be subsequently programmed to any state by writ- ing the liu register regardless of the state of the ds1_cept pin. the ds1_cept pin is only used to determine the reset default state of the equalization bits. liu transmitter alarms loss of liu transmit clock (lotc) alarm a loss of liu transmit clock alarm (lotc = 1, see reg- ister liu_reg0, bit 3) is indicated if any of the clocks used in the liu transmitter paths are absent. this includes loss of tlck-liu input, loss of rlck-liu dur- ing remote loopback, loss of jitter attenuator output clock (when enabled in transmit path), or the internal loss of clock from the pulse-width controller. for all of these conditions, the liu transmitter timing clock is lost and no data can be driven onto the line. output drivers ttip and tring are placed in a high-impedance state when this alarm is active. the lotc alarm asserts between 3 m s and 16 m s after the clock is lost and deasserts immediately after detecting the first clock edge. the lotc alarm status bit will latch the alarm and remain set until being cleared by a read (clear on read). upon the transition from lotc = 0 to lotc = 1, an interrupt will be generated if the lotc interrupt enable bit lotcie (register liu_reg1, bit 3) is set. the reset default is lotcie = 0. an lotc alarm may occur when rloop is activated and deactivated due to the phase transient that occurs as tlck-liu switches its source to and from rlck- liu. setting the rloop alarm prevention prlalm = 1 (register liu_reg4, bit 3) prevents the lotc alarm from occurring at the activation and deactivation of rloop but allows the alarm to operate normally dur- ing the rloop active period. the reset default is prlalm = 0. liu transmitter driver monitor (tdm) alarm the transmit driver monitor detects two conditions: a nonfunctional link due to faults on the primary of the transmit line transformer and periods of no data trans- mission. the tdm alarm (register liu_reg0, bit 2) is the ord function of both faults and provides informa- tion about the integrity of the liu transmitter signal path. * if tlck from the framer is present, automatic transmission of ais upon reset will occur only if the chi common control register frm_pr45 bit 0 = 0, the default, or low-frequency pllck mode. in this case, pllck will be equal to the line transmit rate, either 1.544 mhz for ds1 or 2.048 mhz for cept. 34 34 lucent technologies inc. preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) october 2000 lucent technologies inc. line interface unit: transmit (continued) the first monitoring function is provided to detect non- functional links and protect the liu transmitter from damage. the alarm is set (tdm = 1) when one of the liu transmitter line drivers (ttip or tring) is shorted to power supply or ground, or ttip and tring are shorted together. under these conditions, internal cir- cuitry protects the liu transmitter from damage and excessive power supply current consumption by forcing the ttip and tring output drivers into a high-imped- ance state. the monitor detects faults on the trans- former primary side, but the transformer secondary faults may not be detected. the monitor operates by comparing the line pulses with the transmit inputs. after 32 transmit clock cycles, the liu transmitter is powered up in its normal operating mode. the liu transmitter drivers attempt to correctly transmit the next data bit. if the error persists, tdm remains active to eliminate alarm chatter and the transmitter is again internally protected for another 32 transmit clock cycles. this pro- cess is repeated until the error condition is removed, and then the tdm alarm is deactivated. the tdm alarm status bit will latch the alarm and remain set until being cleared by a read (clear on read). the second monitoring function is to indicate periods of no data transmission. the alarm is set (tdm = 1) when 33 consecutive zeros have been transmitted. the alarm is cleared (tdm = 0) on the detection of a single pulse. this alarm condition does not alter the function- ality of the signal path. upon the transition from tdm = 0 to tdm = 1, a micro- processor interrupt will be generated if the tdm inter- rupt enable bit tdmie (register liu_reg1, bit 2) is set. the reset default is tdmie = 0. a tdm alarm may occur when rloop is activated and deactivated. if the prlalm bit is not set, then rloop may activate an lotc alarm, which will put the output drivers ttip and tring in a high-impedance state as described in loss of liu transmit clock (lotc) alarm. the high-impedance state of the drivers may in turn generate a tdm alarm. setting the highz alarm prevention phizalm = 1 (register liu_reg4, bit 4) prevents the tdm alarm from occurring when the drivers are in a high-imped- ance state. the reset default is phizalm = 0. dsx-1 transmitter pulse template and specifications the ds1 pulse shape template is specified at the dsx (defined by cb119 and ansi t1.102) and is illustrated in figure 10. the liu transmitter also meets the pulse template specified by itu-t g.703 (not shown). 5-1160(f) figure 10. dsx-1 isolated pulse template 1.0 0.5 0 C0.5 0 250 500 750 1000 1250 time (ns) normalized amplitude (a) lucent technologies inc. 35 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. line interface unit: transmit (continued) table 8. dsx-1 pulse template corner points (from cb119, t1.102) during ds1 operation, the liu transmitter ttip and tring pins will perform as specified in table 9. table 9. ds1 transmitter specifications 1. with the line circuitry specified in table 14. 2. total power difference. 3. measured in a 2 khz band around the specified frequency. 4. using lucent transformer 2795b and components in table 14. 5. below the power at 772 khz. maximum curve minimum curve ui ns normalized amplitude ui ns normalized amplitude C0.77 C0.39 C0.27 C0.27 C0.12 0.0 0.27 0.25 0.93 1.16 0 250 325 325 425 500 675 725 1100 1250 0.05 0.05 0.80 1.15 1.15 1.05 1.05 C0.07 0.05 0.05 C0.77 C0.23 C0.23 C0.15 0.0 0.15 0.23 0.23 0.46 0.66 0.93 1.16 0 350 350 400 500 600 650 650 800 925 1100 1250 C0.05 C0.05 0.50 0.95 0.95 0.90 0.50 C0.45 C0.45 C0.20 C0.05 C0.05 parameter min typ max unit specification output pulse amplitude at dsx 1 2.5 3.0 3.5 v at&t cb119, ansi t1.102 output pulse width at line side of transformer 1 325 350 375 ns output pulse width at device pins ttip and tring 1 330 350 370 ns positive/negative pulse imbalance 2 0.10.4db power levels: 3,4 772 khz 12.6 17.9 dbm 1.544 mhz 5 29 39 db preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 36 lucent technologies inc. lucent technologies inc. line interface unit: transmit (continued) cept transmitter pulse template and specifications cept pulse shape template is specified at the system output (defined by itu-t g.703) and is illustrated in figure 11. 5-3145(f) figure 11. itu-t g.703 pulse template 269 ns (244 + 25) 219 ns (244 C 25) 244 ns 194 ns (244 C 50) 20% 488 ns (244 + 244) 20% 20% 10% 10% 10% 10% 0% 50% 10% v = 100% 10% nominal pulse lucent technologies inc. 37 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) lucent technologies inc. line interface unit: transmit (continued) during e1 operation, the liu transmitter ttip and tring pins will perform as specified in table 10. table 10. cept transmitter specifications 1. with the line circuitry specified in table 14, measured at the transformer secondary. 2. using lucent transformer 2795d or 2795c and components in table 14. parameter min typ max unit specification output pulse amplitude 1 : 75 w 120 w 2.13 2.7 2.37 3.0 2.61 3.3 v v itu-t g.703 output pulse width at line side of transformer 1 219 244 269 ns output pulse width at device pins ttip and tring 1 224 244 264 ns positive/negative pulse imbalance: pulse amplitude pulse width C4 C4 1.5 1 4 4 % % zero level (percentage of pulse amplitude) C5 0 5 % return loss: 2 120 w 51 khz to 102 khz 102 khz to 2.048 mhz 2.048 mhz to 3.072 mhz return loss: 2 75 w 51 khz to 102 khz 102 khz to 3.072 mhz 9 15 11 7 9 db db db db db ch-ptt ets 300 166: 1993 line interface unit: jitter attenuator a selectable jitter attenuator is provided for narrow- bandwidth jitter transfer function applications. when placed in the liu receive path, the jitter attenuator pro- vides narrow-bandwidth jitter filtering for line-synchroni- zation. the jitter attenuator can also be placed in the liu transmit path to provide clock smoothing for appli- cations such as synchronous/asynchronous demulti- plexers. in these applications, tlck-liu will have an instantaneous frequency that is higher than the data rate and some tlck-liu periods are suppressed (gapped) in order to set the average long-term tlck- liu frequency to within the transmit line rate specifica- tion. the jitter attenuator will smooth the gapped clock. generated (intrinsic) jitter generated jitter is the amount of jitter appearing on the output port when the applied input signal has no jitter. the jitter attenuator outputs a maximum of 0.04 ui peak-to-peak intrinsic jitter. jitter transfer function the jitter transfer function describes the amount of jitter that is transferred from the input to the output over a range of frequencies. the jitter attenuator exhibits a single-pole roll-off (20 db/decade) jitter transfer charac- teristic that has no peaking and a nominal filter corner frequency (3 db bandwidth) of less than 4 hz for ds1 operation and approximately 10 hz for cept opera- tion. optionally, a lower bandwidth of approximately 1.25 hz can be selected in cept operation by setting jabw0 = 1 (register liu_reg4, bit 5) for systems desiring compliance with etsi-tbr12 and tbr13 jitter attenuation requirements. the reset default is jabw0 = 0. for a given frequency, different jitter amplitudes will cause a slight variation in attenuation because of finite quantization effects. jitter amplitudes of less than approximately 0.2 ui will have greater attenuation than the single-pole roll-off characteristic. the jitter transfer curve is independent of data patterns. typical jitter transfer curves of the jitter attenuator are given in fig- ures 13 and 15. preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 38 lucent technologies inc. lucent technologies inc. line interface unit: jitter attenuator (continued) jitter accommodation the minimum jitter accommodation of the jitter attenuator occurs when the sysck frequency and the input clocks long-term average frequency are at their extreme frequency tolerances. when the jitter attenuator is used in the liu transmit path, the minimum accommodation is 28 ui peak-to-peak at the highest jitter frequency of 15 khz. typical receiver jitter accommodation curves including the jitter attenuator in the liu receive path are given in figures 12 and 14. when the jitter attenuator is placed in the data path, a difference between the sysck/16 frequency and the incom- ing line rate for receive applications, or the tclk rate for transmit applications will result in degraded low- frequency jitter accommodation performance. the peak-to-peak jitter accommodation (japp) for frequencies from above the corner frequency of the jitter attenuator (fc) to approximately 100 hz is given by the following equation: where: fdata = 1.544 mhz for ds1 or 2.048 mhz for e1, for jabw0 = 0, fc = 3.8 hz for ds1 or 10 hz for e1, and for jabw0 = 1, fc = 1.25 hz for e1, yfsysclk = sysck tolerance in ppm, yfdata = data tolerance in ppm. note that for lower corner frequencies the jitter accommodation is more sensitive to clock tolerance than for higher corner frequencies. when jabw0 = 1 and the jitter attenuator is used in the receive data path, the tolerance on sysck should be tightened to 20 ppm in order to meet the jitter accommodation requirements of tbr12/13 as given in g.823 for line data rates of 50 ppm. jitter attenuator enable (transmit or receive path) the jitter attenuator is placed in the liu receive path by setting jar = 1 (register liu_reg3, bit 0). the jitter atten- uator is selected in the liu transmit path by setting jat = 1 (register liu_reg3, bit 1). when jar = 1 and jat = 1 or when jar = 0 and jat = 0, the jitter attenuator is disabled. note that the power consumption increases slightly on a per-channel basis when the jitter attenuator is active. the reset default case is jar = jat = 0. japp 64 2f sysclk dd f data C () f data 2 p f c ----------------------------------------------------------------- - C ? ?? ui = lucent technologies inc. 39 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. line interface unit: jitter attenuator (continued) 5-5264(f) figure 12. t1/ds1 receiver jitter accommodation with jitter attenuator 5-5265(f)r.1 figure 13. t1/ds1 jitter transfer of the jitter attenuator 0.1 ui 1.0 ui 10 ui 100 ui 10 100 1k 10k 1 28 ui frequency (hz) 100k tr-tsy-000009 (ds1, muxes) gr-499/1244-core (cat i interfaces) i.431(ds1), g.824(ds1) typical (subject to device characterization) (non-sonet cat ii interfaces) gr-499-core t1.408/i.431(ds1)/g.824(ds1) 60 40 20 0 1 10 100 1 k 10 k 50 30 10 100 k frequency (hz) jitter out/jitter in (db) ty p i c a l (subject to device characterization) tr-tsy-000009 gr-253-core preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 40 lucent technologies inc. lucent technologies inc. line interface unit: jitter attenuator (continued) 5-5266(f)r.9 figure 14. cept/e1 receiver jitter accommodation with jitter attenuator 5-5267(fr.1 figure 15. cept/e1 jitter transfer of the jitter attenuator 0.1 ui 1.0 ui 10 ui 100 ui 10 100 1k 10k 1 37 ui frequency (hz) g.823 100k typical (subject to device characterization) g.823,ets-300-011a1 i.431(cept)/ets-300-011 i.431(cept)/ets-300-011 jabw0 = 0 jabw0 = 1 frequency (hz) jitter out/jitter in (db) 60 40 20 0 1 10 100 1 k 10 k 50 30 10 100 k ty p i c a l (subject to device characterization) jabw0 = 1 jabw0 = 0 etsi tbr12/13 etsi-300-011 i.431, g.735-9 with jitter reducer g.735-9 at national boundaries lucent technologies inc. 41 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. line interface unit: loopbacks the liu has independent loopback paths that are acti- vated using loopa and loopb control bits (register liu_reg5, bits 2 to 3) as shown in table 10. the loca- tions of these loopbacks are illustrated in figure 5, block diagram of line interface unit: single channel. full local loopback (flloop) a full local loopback (flloop) connects the liu trans- mit driver input to the receive analog front-end circuitry. valid transmit output data continues to be sent to the network. if the liu transmitter ais signal (all-ones sig- nal) is sent to the network, by setting the xlais bit (register liu_reg5, bit 1), the looped data is not affected. the alos alarm continues to monitor the receive line interface signal (rtip and rring) while the dlos alarm monitors the looped data. see digital loss of signal (dlos) alarm section on page 26 regarding the behavior of the dlos alarm upon activation of flloop. remote loopback (rloop) a remote loopback (rloop) connects the recovered clock and retimed data to the liu transmitter at the framer interface and sends the data back to the line. the liu receiver front end, clock/data recovery, encoder/decoder (if enabled), jitter attenuator (if enabled), and liu transmitter driver circuitry are all exercised during this loopback. the transmit clock, transmit data, and the transmit ais inputs are ignored. valid receive output data continues to be sent to rpd- liu and rnd-liu. this loopback mode is very helpful in isolating failures between systems. see loss of liu transmit clock (lotc) alarm section and liu transmitter driver monitor on page 33 regard- ing the behavior of the lotc and tdm alarms upon activation and deactivation of rloop. digital local loopback (dlloop) a digital local loopback (dlloop) connects the trans- mit clock and data through the encoder/decoder pair to the receive clock and data output pins. this loopback is operational regardless of whether the encoder/decoder pair is enabled or disabled. the alarm indication signal can be transmitted (xlais = 1) without any effect on the looped signal. table 11. loopback control 1. the reset default condition is loopa = loopb = 0 (no loopback). 2. during the transmit ais condition, the looped data will be the transmitted data from the framer or system interface and not the all ones signal. 3. transmit ais request is ignored. line interface unit: other features liu powerdown (pwrdn) each liu channel has an independent powerdown mode controlled by pwrdn (register liu_reg5, bit 0). this provides power savings for systems which use backup channels. if pwrdn = 1, the correspond- ing liu channel will be in a standby mode consuming only a small amount of power. it is recommended that the alarm registers for the powered down liu channel be disabled by setting alosie = dlosie = tdmie = lotcie = 0 (register liu_reg1, bits 03). if an liu channel in powerdown mode needs to be placed back into service, the channel should be turned on (pwrdn = 0) approximately 5 ms before data is applied. loss of framer receive line clock (lofrm- rlck pin) the lofrmrlck (pin 2/38) is set when the internal framer receive line clock is absent. during this alarm condition, the clock recovery and jitter attenuator func- tions are automatically disabled. if jar = 1, the rlck- liu, rpd-liu, rnd-liu, and dlos signals will be unknown. in-circuit testing and driver high-imped- ance state (3-state ) if 3-stat e (pin 42/140) is activated (3-state = 0), the outputs ttip, tring, rdy_dtack , interrupt, and ad[7:0] are placed in a high-impedance state. the ttip and tring outputs have a limiting high-imped- ance capability of approximately 8 k w . operation symbol loopa loopb normal 1 00 full local loopback flloop 2 01 remote loopback rloop 3 10 digital local loopback dlloop 1 1 preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 42 lucent technologies inc. lucent technologies inc. line interface unit: other features (continued) liu delay values the transmit coder has 5 ui delay whether it is in the path or not and whether it is b8zs or hdb3. its delay is only removed when in single-rail mode. the remainder of the transmit path has 4.6 ui delay. the receive decoder has five ui delay whether it is in the path or not and whether it is b8zs or hdb3. its delay is only removed when in single-rail mode or cdr = 0. the equalizer plus slicer delay is nearly 0 ui delay. the jitter attenuator delay is nominally 33 ui but can be 2 ui 64 ui depending on state. the digital phase-locked loop used for timing recovery has 8 ui delay. sysck reference clock the liu requires an externally applied clock, sysck pins 3 and 35, for the clock and data recovery function and the jitter attenuation option. sysck must be a con- tinuously active (i.e., ungapped, unjittered, and unswitched) and an independent reference clock such as from an external system oscillator or system clock for proper operation. it must not be derived from any recovered line clock (i.e., from rlck or any synthe- sized frequency of rlck). sysck may be supplied in one of two formats. the for- mat is selected for each channel by cksel pins 48 and 133. for cksel = 1, a clock at 16x the primary line data rate clock (24.704 mhz for ds1 and 32.768 mhz for cept) is applied to sysck. for cksel = 0, a primary line data rate clock (1.544 mhz for ds1 and 2.048 mhz for cept) is applied to sysck. the cksel pin has an internal pull-up resistor allowing the pin to be left open, i.e., a no connect, in applica- tions using a 16x reference clock and pulled down to ground for applications using a primary line data rate clock. 16x sysck reference clock the specifications for sysck using a 16x reference clock are defined in table 12. the 16x reference clock is selected when cksel = 1. table 12. sysck (16x, cksel = 1) timing specifications * when jabw0 = 1 and the jitter attenuator is used in the receive data path, the tolerance on sysck should be tightened to 20 ppm in order to meet the jitter accommodation requirements of tbr12/ 13 as given in g.823 for line data rates of 50 ppm. ? if sysck is used as the source for ais (see liu transmitter alarm indication signal generator (xlais)), it must meet the nominal transmission specifications of 1.544 mhz 32 ppm for ds1 (t1) or 2.048 mhz 50 ppm for cept (e1). primary line rate sysck reference clock and internal reference clock synthesizer in some applications, it is more desirable to provide a reference clock at the primary data rate. in such cases, the liu can utilize an internal 16x clock synthesizer allowing the sysck pin to accept a primary data rate clock. the specifications for sysck using a primary rate reference clock are defined in table 13. table 13. sysck (1x, cksel = 0) timing specifications * when jabw0 = 1 and the jitter attenuator is used in the receive data path, the tolerance on sysck should be tightened to 20 ppm in order to meet the jitter accommodation requirements of tbr12/ 13 as given in g.823 for line data rates of 50 ppm. ? if sysck is used as the source for ais (see liu transmitter alarm indication signal generator (xlais)), it must meet the nominal transmission specifications of 1.544 mhz 32 ppm for ds1 (t1), or 2.048 mhz 50 ppm for cept (e1). parameter value unit min typ max frequency ds1 cept 24.704 32.768 mhz mhz range*, ? C100 100 ppm duty cycle 40 60 % parameter value unit min typ max frequency ds1 cept 1.544 2.048 mhz mhz range*, ? C100 100 ppm duty cycle 40 60 % rise and fall times (10%90%) 5ns lucent technologies inc. 43 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. sysck reference clock (continued) the data rate reference clock and the internal clock synthesizer is selected when cksel = 0. in this mode, a valid and stable data rate reference clock must be applied to the sysck pin before and during the time a hardware reset is activated (reset = 0). the reset must be held active for a minimum of two data rate clock periods to ensure proper resetting of the clock synthesizer circuit. upon the deactivation of the reset pin (reset = 1), the liu will extend the reset condition internally for approximately 1/2(2 12 C 1) line clock peri- ods, or 1.3 ms for ds1 and 1 ms for cept after the hardware reset pin has become inactive allowing the clock synthesizer additional time to settle. no activity such as microprocessor read/write should be per- formed during this period. the device will be opera- tional 2.7 ms after the deactivation of the hardware reset pin. issuing an liu software restart (liu_reg2 bit 5 (restart) = 1) does not impact the clock synthe- sizer circuit. line interface unit: line interface networks the transmit and receive tip and ring connections pro- vide a matched interface to the line cable when used with a proper matching network. the diagram in figure 16 shows the appropriate external components to interface to the cable for a single transmit/receive chan- nel. the component values are summarized in table 14, based on the specific application. 5-3693(f).d figure 16. line termination circuitry rtip rring ttip tring device (1 channel) r l r s r r r r receive data r p z eq r t r t n:1 transmit data transformer equipment interface 1:n c c c p preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 44 lucent technologies inc. lucent technologies inc. line interface unit: line interface networks (continued) table 14. termination components by application 1 1. resistor tolerances are 1%. transformer turns ratio tolerances are 2%. 2. use lucent 2795b transformer. 3. for cept 75 w applications, option 1 is recommended over option 2 for lower device power dissipation. option 2 increases power dissipa- tion by 13 mw per channel when driving 50% ones data. option 2 allows for the use of the same transformer as in cept 120 w applications. 4. use lucent 2795d transformer. 5. use lucent 2795c transformer. 6. a 5% tolerance is allowed for the transmit load termination. the transmit and receive tip and ring connections should be provided with a matched and protected interface to the line (i.e., terminating impedance to match the characteristic impedance of the line cable and secondary line protec- tion). for the purpose of line protection and matching network design, the equivalent input impedance of the receiver and the equivalent output circuit of the transmitter can be assumed to be as shown in figure 17. symbol name cable type unit ds1 2 twisted pair cept 75 w 3 coaxial cept 120 w 5 twisted pair option 1 4 option 2 5 c c center tap capacitor 0.1 0.1 0.1 0.1 m f r p receive primary impedance 200 200 200 200 w r r receive series impedance 71.5 28.7 59 174 r s receive secondary impedance 113 82.5 102 205 z eq equivalent line termination 100 75 75 120 tolerance 4 4 4 4 % r t transmit series impedance 0 26.1 15.4 26.1 w r l transmit load termination 6 100 75 75 120 n transformer turns ratio 1.14 1.08 1.36 1.36 lucent technologies inc. 45 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. line interface unit: line interface networks (continued) 5-6232(f).ar.5 * approximately 0.3 v2.0 v peak. ? approximate pulse voltage source (peak). figure 17. T7630 line interface unit approximate equivalent analog i/o circuits mode peak unit ds1 3.0 v cept: 75 w : option 1 option 2 120 w 4.2 3.4 4.2 v v v receiver pulse voltage source ? transmitter output 2 w 2.5 w 47 k w 2 pf 20 k w input* a. receiver input approximate equivalent circuit b. transmitter output approximate equivalent circuit 2 w 2.5 w 3 pf 20 k w 3 pf grnd a preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 46 lucent technologies inc. lucent technologies inc. liu-framer interface liu-framer physical interface the transmit framer-liu interface for the T7630 consists of the tnd, tpd, and tlck pins. in normal operations, tnd, tpd, and tlck are directly connected to the transmit line interface and the tpd, tnd, and tlck pins are driven from the transmit framer. the receive framer-liu interface for the T7630 consists of the rpd, rnd_bpv, and rlck internal signals. in normal operations, rnd, rpd, and rlck are directly sourced from the internal receive line interface unit. in the framer mode, framer = 0, the rpd, rnd, and rlck pins are directly connected to the receive framer (the internal receive line interface unit is bypassed). figure 18 illustrates the interfaces of the transmit and receive framer units. 5-4557(f).br.2 figure 18. block diagram of framer line interface ttip tring transmit line interface unit tlck tnd tpd tlck tpd tnd transmit framer transmit hdlc facil ity data link interface receive concentration highway interface tfdlck tfdl rchidata rchick receive hdlc facilit y data link interface receive framer 1 0 rlck rpd rnd_bpv rtip rring receive line interface unit framer transmit concentration highway interface tchidata rfdlck rfdl (xliu) (xfrmr) (rchi) (xchi) (rfrmr) (rliu) line interface system interface pllck tchifs tchick rfrmck liu_rlck liu_rnd/bpv liu_rpd frm_rlck frm_rnd frm_rpd rchifs lucent technologies inc. 47 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) lucent technologies inc. liu-framer interface (continued) figure 19 shows the timing requirements for the transmit and receive framer interfaces in the liu-bypass mode. 5-4558(f).cr.3 figure 19. transmit framer tlck to tnd, tpd and receive framer rnd, rpd to rlck timing 162 ns t1-ds1 648 ns t1 t2r-f t2f-r t3 t4 t5 pllck tlck tnd, tpd rlck rnd, rpd rfrmck t7 = rpd, rnd hold from rising rlck = 40 ns t6 t7 t8 t2r-f: t2f-r: pllck to tlck delay = 50 ns t3-ds1 = 648 ns t3-cept = 488 ns t4 = tlck to valid tpd, tnd = 30 ns t5-cept = 488 ns t5-ds1 = 648 ns t6 = rpd, rnd setup to rising rlck = 40 ns t8r-f: t8f-r: rlck to rfrmck delay = 50 ns frm_pr45 bit 0 (hflf) hflf = 0 hflf = 1 122 ns t1-cept 488 ns interface mode and line encoding single rail the default mode for the liu-framer interface is single- rail, register liu_reg3 bit 3 (dual) = 0 and register frm_pr8 bit 7 = 1, bit 6 = 1, and bit 5 = 0. in the single-rail terminator mode (framer = 1), the liu bipolar encoder and decoder may be enabled by setting register liu_reg3 bit 2 (code) to 1. signals passed on the internal liu-framer interface are data (liu_rpd and tpd), clock (liu_rlck and tlck), and received bipolar violations (liu_rnd/bpv). when liu_rnd/bpv = 1, the bpv counter increments by one on the rising edge of liu_rlck. in the single-rail framer mode (framer = 0), external signals to and from the framer are data (rtip_rpd, pin 11/27 and tpd, pin 44/138), clock (rlck, pin 47/135 and tlck, pin 46/136), and received bipolar violations (rring_rnd, pin 10/28). when rring_rnd = 1, the bpv counter increments by one on the rising edge of rlck. in this mode, tnd (pin 45/137) is forced to the 0 state. dual rail dual-rail liu-framer interface mode is selected by set- ting liu_reg3 bit 3 (dual) = 1 and by selecting one of the dual-rail framer modes of frm_pr8 bit 5bit 7. in the dual-rail terminator mode (framer = 1), the framer bipolar encoder and decoder are enabled. sig- nals passed on the internal liu-framer interface are data (liu_rpd, liu_rnd, tpd, and tnd), and clock (liu_rlck and tlck). when bipolar violations are detected by the framer, the bpv counter increments by one on the rising edge of liu_rlck. in the dual-rail framer mode (framer = 0), external signals to and from the framer are data (rtip_rpd, pin 11/27; rring_rnd, pin 10/28; tpd, pin 44/138; and tnd, pin 45/137) and clock (rlck, pin 47/135 and tlck, pin 46/136). when bipolar violations are detected by the framer, the bpv counter increments by one on the rising edge of rlck. preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 48 lucent technologies inc. lucent technologies inc. liu-framer interface (continued) ds1: alternate mark inversion (ami) the default line code used for t1 is alternate mark inversion (ami). the coding scheme represents a one with a pulse (mark) on the positive or negative rail and a zero with no pulse on either rail. this scheme is shown in table 15. table 15. ami encoding the t1 ones density rule states that: in every 24 bits of information to be transmitted, there must be at least three pulses, and no more than 15 zeros may be transmitted consecutively [at&t tr62411 (1988), ansi t1.231 (1997)]. receive ones density is monitored by the receive line interface as per t1m1.3/93-005, itu g.775, or tr-tsy- 000009. the receive framer indicates excessive zeros upon detecting any zero string length greater than 15 contiguous zeros (no pulses on either rpd or rnd). both excessive zeros and coding violations are indicated as bipolar viola- tions. ds1: zero code suppression (zcs) zero code suppression is a technique known as pulse stuffing in which the seventh bit of each time slot is stuffed with a one. the line format (shown in table 16) limits the data rate of each time slot from 64 kbits/s to 56 kbits/s. the default zcs format stuffs the seventh bit of those all-zero time slots programmed for robbed-bit signaling (as defined in the signaling control registers with the f and g bits). the receive framer indicates excessive zeros upon detecting any zero string length greater than fifteen contiguous zeros (no pulses on either rpd or rnd). both excessive zeros and coding violations are indicated as bipolar viola- tions. table 16. ds1 zcs encoding ds1: binary 8 zero code suppression (b8zs) clear channel transmission can be accomplished using binary 8 zero code suppression (b8zs). eight consecu- tive zeros are replaced with the b8zs code. this code consists of two bipolar violations in bit positions four and seven and valid bipolar marks in bit positions five and eight. the receiving end recognizes this code and replaces it with the original string of eight zeros. the receive framer indicates excessive zeros upon detecting a block of eight or more consecutive zeros (no pulses on either rpd or rnd). both excessive zeros and coding violations are indicated as bipolar violations. input bit stream 1011 0000 0111 1010 ami data C0+C 0000 0+C+ C0+0 input bit stream 00000000 01010000 00000000 00000000 zcs data (framer mode) 00000010 01010010 00000010 00000010 T7630 default zcs 00000010 01010000 00000000 (data time slot remains clear) 00000010 lucent technologies inc. 49 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. liu-framer interface (continued) table 17 shows the encoding of a string of zeros using b8zs. b8zs is recommended when esf format is used. v represents a violation of the bipolar rule, and b represents an inserted pulse conforming to the ami rule. table 17. ds1 b8zs encoding cept: high-density bipolar of order 3 (hdb3) the line code used for cept is described in itu rec. g.703 section 6.1 as high-density bipolar of order 3 (hdb3). hdb3 uses a substitution code that acts on strings of four zeros. the substitute hdb3 codes are 000v and b00v, where v represents a violation of the bipolar rule and b represents an inserted pulse conforming to the ami rule defined in itu rec. g.701, item 9004. the choice of the b00v or 000v is made so that the number of b pulses between consecutive v pulses is odd. in other words, successive v pulses are of alternate polarity so that no direct current (dc) component is introduced. the substitute codes follow each other if the string of zeros continues. the choice of the first substitute code is arbitrary. a line code error consists of two pulses of the same polarity that is not defined as one of the two substitute codes. excessive zeros consist of any zero string length greater than four con- tiguous zeros. both excessive zeros and coding violations are indicated as bipolar violations. an example is shown in table 18. table 18. itu hdb3 coding frame formats the supported north american t1 framing formats are superframe (d4, slc -96, and digital data service-dds) and extended superframe (esf). the device can be programmed to support the itu-cept-e1 basic format with and without crc-4 multiframe formatting. this section describes these framing formats. t1 framing structures t1 is a digital transmission system which multiplexes twenty-four 64 kbits/s time slots (ds0) onto a serial link. the t1 system is the lowest level of hierarchy on the north american t-carrier system, as shown in figure 20. table 19. t-carrier hierarchy bit positions 1234567812345678 before b8zs 0000000010100000000 after b8zs 000vb0vbb0b000vb0vb input bit stream 1011 0000 01 0000 0000 0000 0000 hdb3-coded data 1011 000v 01 000v b00v b00v b00v hdb3-coded levels C0+C 000C 0+ 000+ C00C +00+ C00C hdb3 with 5 double bpvs C0+C C000 0+ +00+ 0CC C +00+ C00C 1-bpv 3-bpv 5-bpv t carrier ds0 channels bit rate (mbits/s) digital signal level t1 24 1.544 ds1 t1-c 48 3.152 ds1c t2 96 6.312 ds2 t3 672 44.736 ds3 t4 4032 274.176 ds4 preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 50 lucent technologies inc. lucent technologies inc. frame formats (continued) frame, superframe, and extended superframe definitions each time slot (ds0) is an assembly of 8 bits sampled every 125 s. the data rate is 64 kbits/s and the sample rate is 8 khz. time-division multiplexing 24 ds0 time slots together produces a 192-bit (24 dszeros) frame. a framing bit is added to the beginning of each frame to allow for detection of frame boundaries and the transport of addi- tional maintenance information. this 193-bit frame, also referred to as a ds1 frame, is repeated every 125 s to yield the 1.544 mbits/s t1 data rate. ds1 frames are bundled together to form superframes or extended super- frames. 5-4559(f).br.1 figure 20. t1 frame structure transparent framing format the transmit framer can be programmed to transparently transmit 193 bits of system data to the line. the system interface must be programmed such that the stuffed time slots are 1, 5, 9, 13, 17, 21, 25, and 29 (frm_pr43 bits 20 must be set to 000) and either transparent framing mode one or transparent framing mode two is enabled (frm_pr26 bit 3 or bit 4 must be set to 1). in transparent mode one or mode two, the transmit framer extracts from the receive system data bit 8 of time slot 1 and inserts this bit into the framing bit position of the transmit line data. the other 7 bits of the receive system time slot 1 are ignored by the transmit framer. the receive framer will extract the f-bit (or 193rd bit) of the receive line data and insert it into bit 7 of time slot one of the system data; the other bits of time slot 1 are set to 0. frame integrity is maintained in both the transmit and receive framer sections. frame 1 frame 2 frame 3 frame 24 frame 23 frame 1 frame 2 frame 11 frame 12 f bit time slot 1 time slot 2 time slot 24 123 45 678 24-frame extended esf = 3.0 ms 12-frame superframe sf = 1.5 ms 193-bit frame ds1 = 125 m s 8-bit time slot ds0 = 5.19 m s superframe lucent technologies inc. 51 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. frame formats (continued) 5-5989(f).ar.1 figure 21. t1 transparent frame structure in transparent framing mode 1, the receive framer is forced not to reframe on the receive line data. other than bipolar violations and unframed ais monitoring, there is no processing of the receive line data. the receive framer will insert the 193rd bit of the receive line data into bit 8 of time slot 1 of the transmit system data. in transparent framing mode 2, the receive framer functions normally on receive line data. all normal monitoring of receive line data is performed and data is passed to the transmit chi as programmed. the receive framer will insert the extracted framing bit of the receive line data into bit 8 of time slot 1 of the transmit system data. the remaining bits in time slot 1 are set to zero. time slot 1 (stuff time slot) 32 time-slot chi frame time slot 2 time slot 3 time slot 31 time slot 32 0000000f bit tramsmit framers 193-bit frame ds1 = 125 m s time slot 1 time slot 2 time slot 24 f bit preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 52 lucent technologies inc. lucent technologies inc. frame formats (continued) d4 frame format d4 superframe format consists of 12 ds1 frames. table 20 shows the structure of the d4 superframe. table 20. d4 superframe format 1. frame 1 is transmitted first. 2. following ansi t1.403, the bits are numbered 02315. bit 0 is transmitted first. bits in each ds0 time slot are numbered 1 through 8, and bit 1 of each ds0 is transmitted first. 3. the remote alarm forces bit 2 of each time slot to a 0-state when enabled. the japanese remote alarm forces framing bit 12 ( bit number 2123) to a 1-state when enabled. 4. signaling option none uses bit 8 for traffic data. 5. frames 6 and 12 contain the robbed-bit signaling information in bit 8 of each voice channel, when enabled. the receive framer uses both the f t and f s framing bits during its frame alignment procedure. digital data service (dds) frame format the superframe format for dds is the same as that given for d4. dds is intended to be used for data-only traffic, and as such, the system should ensure that the framer is in the nonsignaling mode. dds uses time slot 24 (fas channel) to transmit the remote frame alarm and data link bits. the format for time slot 24 is shown in table 21. the facility data link timing is shown in figure 22 below. table 21. dds channel-24 format frame framing bits bit used in each time slot signaling options number 1 bit number 2 terminal frame f t signal frame f s tr affic (all channels) remote alarm 3 signaling none 4 2-state 4-state 10 1 18 2 2193 0 18 2 3386 0 18 2 4579 0 18 2 5772 1 18 2 6 5 965 1 17 2 8 a a 7 1158 0 18 2 8 1351 1 18 2 9 1544 1 18 2 10 1737 1 18 2 11 1930 0 18 2 12 5 2123 0 17 2 8 a b time slot 24 = 10111yd0 y = (bit 6) remote frame alarm: 1 = no alarm state; 0 = alarm state d = (bit 7) data link bits (8 kbits/s) lucent technologies inc. 53 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. frame formats (continued) 5-3910(f).cr.1 figure 22. T7630 facility data link access timing of the transmit and receive framer sections slc -96 frame format slc -96 superframe format consists of 12 ds1 frames similar to d4. the ft pattern is exactly the same as d4. the fs pattern uses that same structure as d4 but also incorporates a 24-bit data link word as shown below. 5-6421(f)r.1 figure 23. fs pattern slc -96 superframe format t8 t9 t9 t10 t11 t8: tfdlck cycle = t9: tfdl to tfdlck setup/hold = 40 ns t10: rfdlck cycle = t11: rfdlck to rfdl delay = 40 ns tfdlck tfdl rfdlck rfdl 250 m s (all other modes) 125 m s (dds) 250 m s (all other modes) 125 m s (dds) fs = . . . 000111000111d 1 ddddddddddddddddddddddd 24 000111000111ddd . . . slc -96 24-bit data link word slc -96 36-frame d-bit superframe interval (72 ds1 frames) frame n C1 frame n frame n + 1 frame n + 2 frame n + 3 frame n + 4 frame n + 5 frame n + 6 frame n + 7 frame n + 8 preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 54 lucent technologies inc. lucent technologies inc. frame formats (continued) external tfdl source. data may be inserted and extracted from the slc -96 data link from either the external facility data link (tfdl) ports or the slc -96 data stack. source selection is controlled by frm_pr21 bit 6 and frm_pr29 bit 5bit 7. the transmit framer synchronizes on tfdl = 000111000111 . . . and forces a superframe boundary based on this pattern. when sourcing an external bit stream, it is the systems responsibility to ensure that tfdl data contain the pattern of 000111000111 . . . . the d pattern sequence is shown in table 22. table 23 shows the encoding for the line switch field. table 22. slc -96 data link block format data link block bit definition bit value d 1 (leftmost bit) c 1 concentrator bit 0 or 1 d 2 c 2 concentrator bit 0 or 1 d 3 c 3 concentrator bit 0 or 1 d 4 c 4 concentrator bit 0 or 1 d 5 c 5 concentrator bit 0 or 1 d 6 c 6 concentrator bit 0 or 1 d 7 c 7 concentrator bit 0 or 1 d 8 c 8 concentrator bit 0 or 1 d 9 c 9 concentrator bit 0 or 1 d 10 c 10 concentrator bit 0 or 1 d 11 c 11 concentrator bit 0 or 1 d 12 spoiler bit 1 0 d 13 spoiler bit 2 1 d 14 spoiler bit 3 0 d 15 m 1 maintenance bit 0 or 1 d 16 m 2 maintenance bit 0 or 1 d 17 m 3 maintenance bit 0 or 1 d 18 a1alarm bit 0 or 1 d 19 a2alarm bit 0 or 1 d 20 s 1 line-switch bit defined in table 23 d 21 s 2 line-switch bit defined in table 23 d 22 s 3 line-switch bit defined in table 23 d 23 s 4 line-switch bit defined in table 23 d 24 (rightmost bit) spoiler bit 4 1 lucent technologies inc. 55 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) lucent technologies inc. frame formats (continued) table 23. slc -96 line switch message codes internal slc -96 stack source. optionally, a slc -96 fdl stack may be used to insert and correspondingly extract the fdl information in the slc -96 frame format. the transmit slc -96 fdl bits are sourced from the transmit framer slc -96 fdl stack. the slc -96 fdl stack (see frm_pr31frm_pr35) consists of five 8-bit registers that contain the slc -96 fs and d-bit information as shown in table 24. the transmit stack data is transmitted to the line when the stack enable mode is active in the parameter registers frm_pr21 bit 6 = 1 and frm_pr29 bit 5bit 7 = x10 (binary). the receive slc -96 stack data is received when the receive framer is in the superframe alignment state. in the slc -96 mode, while in the loss of superframe alignment (lsfa) state, updating of the receive framer slc -96 stack is halted and neither the receive stack interrupt nor receive stack flag are asserted. table 24. transmit and receive slc -96 stack structure s 1 s 2 s 3 s 4 code definition 1111 idle 1110 switch line a receive 1101 switch line b transmit 1100 switch line c transmit 1010 switch line d transmit 0101switch line b transmit and receive 0100switch line b transmit and receive 0010switch line b transmit and receive register number bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) 1 (lsr)00000111 2 00000111 3c 1 c 2 c 3 c 4 c 5 c 6 c 7 c 8 4c 9 c 10 c 11 spb 1 = 0 spb 2 = 1 spb 3 = 0 m 1 m 2 5m 3 a 1 a 2 s 1 s 2 s 3 s 4 spb 4 = 1 bit 5bit 0 of the first 2 bytes of the slc -96 fdl stack in table 24 are transmitted to the line as the slc -96 f s sequence. bit 7 of the third stack register is transmitted as the c 1 bit of the slc -96 d sequence. the spoiler bits (spb1, spb2, spb3, and spb4) are taken directly from the transmit stack. the protocol for accessing the slc -96 stack information for the transmit and receive framer is described below. the transmit slc -96 stack must be written with valid data when transmitting stack data. the device indicates that it is ready for an update of its transmit stack by setting register frm_sr4 bit 5 ( slc - 96 transmit fdl stack ready) high. at this time, the sys- tem has about 9 ms to update the stack. data written to the stack during this interval will be transmitted during the next slc -96 superframe d-bit interval. by reading bit 5 in register sr4, the system clears this bit so that it can indicate the next time the transmit stack is ready. if the transmit stack is not updated, then the content of the stack is retransmitted to the line. the start of the slc -96 36-frame f s interval of the transmit framer is a function of the first 2 bytes of the slc -96 transmit stack registers. these bytes must be programmed as shown in table 24. programming any other state into these two registers disables the proper transmission of the slc -96 d bits. once programmed correctly, the trans- mit slc -96 d-bit stack is transmitted synchronous to the transmit slc -96 superframe structure. on the receive side, the device indicates that it has received data in the receive fdl stack (registers frm_sr54frm_sr58) by setting bit 4 in register frm_sr4 ( slc -96 receive fdl stack ready) high. the system then has about 9 ms to read the content of the stack before it is updated again (old data lost). by read- ing bit 4 in register frm_sr4, the system clears this bit so that it can indicate the next time the receive stack is ready. as explained above, the slc -96 receive stack is not updated when superframe alignment is lost. preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 56 lucent technologies inc. lucent technologies inc. frame formats (continued) extended superframe format the extended superframe format consists of 24 ds1 frames. the f bits are used for frame alignment, superframe alignment, error checking, and facility data link transport. table 25 shows the esf frame format. table 25. extended superframe (esf) structure 1. frame 1 is transmitted first. 2. the remote alarm is a repeated 1111111100000000 pattern in the dl when enabled. 3. following ansi t1.403, the bits are numbered 04361. bit 0 is transmitted first. bits in each ds0 time slot are numbered 1 through 8, and bit 1 of each ds0 is transmitted first. 4. the c 1 to c 6 bits are the cyclic redundancy check-6 (crc-6) checksum bits calculated over the previous extended superframe. 5. signaling option none uses bit 8 for traffic data. 6. frames 6, 12, 18, and 24 contain the robbed-bit signaling information in bit 8 of each voice channel, when enabled. the esf format allows for in-service error detection and diagnostics on t1 circuits. esf format consist of 24 fram- ing bits: six for framing synchronization (2 kbits/s); six for error detection (2 kbits/s); and 12 for in-service monitoring and diagnostics (4 kbits/s). frame number 1 frame bit bit use in each time slot signaling option 2 bit number 3 f e d l crc- 6 4 traffic signaling none 5 2-state 4-state 16-state 1 0 d 18 2 193 c 1 18 3 386 d 18 4 579 0 18 5 772 d 18 6 6 965 c 2 17 8 a a a 7 1158 d 18 8 1351 0 18 9 1544 d 18 10 1737 c 3 18 11 1930 d 18 12 6 2123 1 17 8 a b b 13 2316 d 18 14 2509 c 4 18 15 2702 d 18 16 2895 0 18 17 3088 d 18 18 6 3281 c 5 17 8 a a c 19 3474 d 18 20 3667 1 18 21 3860 d 18 22 4053 c 6 18 23 4246 d 18 24 6 4439 1 17 8 a b d lucent technologies inc. 57 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. frame formats (continued) cyclic redundancy checking is performed over the entire esf data payload (4,608 data bits, with all 24 framing bits (f e , d l , crc-6) set to one during calculations). the crc-6 bits transmitted in esf will be determined as follows: n the check bits, c1 through c6, contained in esf( n + 1) will always be those associated with the contents of esf( n ), the immediately preceding esf. when there is no esf immediately preceding, the check bits may be assigned any value. n for the purpose of crc-6 calculation only, every f bit in esf( n ) is set to 1. esf( n ) is altered in no other way. n the resulting 4632 bits of esf( n ) are used, in order of occurrence, to construct a polynomial in x such that the first bit of esf( n ) is the coefficient of the term x 4631 and the last bit of esf( n ) is the coefficient of the term x 0 . n the polynomial is multiplied by the factor x 6 , and the result is divided, modulo 2, by the generator polynomial x 6 + x + 1. the coefficients of the remainder polynomial are used, in order of occurrence, as the ordered set of check bits, c1 through c6, that are transmitted in esf( n + 1). the ordering is such that the coefficient of the term x 5 in the remainder polynomial is check bit c1 and the coefficient of the term x 0 in the remainder polynomial is check bit c6. the esf remote frame alarm consists of a repeated eight ones followed by eight zeros transmitted in the data link position of the framing bits. t1 loss of frame alignment (lfa) loss of frame alignment condition for the superframe or the extended superframe formats is caused by the inability of the receive framer to maintain the proper sequence of frame bits. the number of errored framing bits required to detect a loss of frame alignment is given is table 26. table 26. t1 loss of frame alignment criteria the receive framer indicates the loss of frame and superframe conditions by setting the lfa and lsfa bits (frm_sr1 bit 0 and bit 1), respectively, in the status registers for the duration of the conditions. the local system may give indication of its lfa state to the remote end by transmitting a remote frame alarm (rfa). in addition, in the lfa state, the system may transmit an alarm indication signal (ais) to the system interface. format number of errored framing bits that will cause a loss of frame alignment condition d4 2 errored frame bits (f t or f s ) out of 4 consecutive frame bits if frm_pr10 bit 2 = 1. 2 errored f t bits out of 4 consecutive f t bits if prm_pr10 bit 2 = 0. slc -96 2 errored frame bits (f t or f s ) out of 4 consecutive frame bits if frm_pr10 bit 2 = 1. 2 errored f t bits out of 4 consecutive f t bits if frm_pr10 bit 2 = 0. dds: frame 3 errored frame bits (f t or f s ) or channel 24 fas pattern out of 12 consecutive frame bits. esf 2 errored f e bits out of 4 consecutive f e bits or optionally 320 or more crc-6 errored check- sums within a one second interval if loss of frame alignment due to excessive crc-6 errors is enabled in frm_pr9. preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 58 lucent technologies inc. lucent technologies inc. frame formats (continued) t1 frame recovery alignment algorithms when in a loss of frame alignment state, the receive framer searches for a new frame alignment and forces its inter- nal circuitry to this new alignment. the receive framers synchronization circuit inhibits realignment in t1 framing formats when repetitive data patterns emulate the t1 frame alignment patterns. t1 frame synchronization will not occur until all frame sequence emulating patterns disappear and only one valid pattern exists. the loss of frame alignment state will always force a loss of superframe alignment state. superframe alignment is established only after frame alignment has been determined in the d4 and slc -96 frame format. table 27 gives the requirements for establishing t1 frame and superframe alignment. table 27. t1 frame alignment procedures frame format alignment procedure d4: frame using the f t frame position as the starting point, frame alignment is established when 24 consecutive f t and f s frame bits, excluding the twelfth f s bit, (48 total frames) are received error-free. once frame alignment is established, then super- frame alignment is determined. d4: superframe after frame alignment is determined, two valid superframe bit sequences using the f s bits must be received error-free to establish superframe alignment. slc -96: frame using the f t frame position as the starting point, frame alignment is established when 24 consecutive f t frame bits (48 total frames) are received error-free. once frame alignment is established, then superframe alignment is determined. slc -96: superframe after frame alignment is determined, superframe alignment is established on the first valid superframe bit sequence 000111000111. dds: frame using the f t frame position as the starting point, frame alignment is established when six consecutive f t /f s frame bits and the dds fas in time slot 24 are received error-free. in the dds format, there is no search for a superframe structure. esf frame and superframe alignment is established simultaneously using the f e fram- ing bit. alignment is established when 24 consecutive f e bits are received error- free. once frame/superframe alignment is established, the crc-6 receive monitor is enabled. lucent technologies inc. 59 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. frame formats (continued) t1 robbed-bit signaling to enable signaling, register frm_pr44 bit 0 (tsig) must be set to 0. robbed-bit signaling, used in either esf or sf framing formats, robs the eighth bit of the voice channels of every sixth frame. the signaling bits are designated a, b, c, and d, depending on the signaling format used. the robbed- bit signaling format used is defined by the state of the f and g bits in the signaling registers (see ds1: robbed-bit signaling). the received channel robbed-bit signaling format is defined by the corresponding transmit signaling f and g bits. table 28 shows the state of the transmitted signaling bits as a function of the f and g bits. table 28. robbed-bit signaling options * see register frm_pr43 bit 3 and bit 4. the robbed-bit signaling format for each of the 24 t1 transmit channels is programmed on a per-channel basis by setting the f and g bits in the transmit signaling direction. slc -96 9-state signaling slc -96 9-state signaling state is enabled by setting both the f and g bits in the signaling registers to the 0 state, setting the slc -96 signaling control register frm_pr43 bit 3 to 1, and setting register frm_pr44 bit 0 to 0. table 29 shows the state of the transmitted signaling bits to the line as a function of the a, b, c and d bit settings in the transmit signaling registers. in table 29 below, x indicates either a 1 or a 0 state, and t indicates a toggle, transition from either 0 to 1 or 1 to 0, of the transmitted signaling bit. in the line receive direction, this signaling mode functions identically to the preceding transmit path description. table 29 . slc -96 9-state signaling format g f robbed-bit signaling format frame 6121824 0 0 esf: 16-state slc *: 9-state, 16-state abcd 01 4-state abab 1 0 data channel (no signaling) payload data 11 2-state aaaa transmit signaling register settings transmit to the line signal bits slc -96 signaling statesabcda = f(a,c)b = f(b,d) state 1 0000 0 0 state 2 0001 0 t state 3 010x 0 1 state 4 0010 t 0 state 5 0011 t t state 6 011x t 1 state 7 1 0 x 0 1 0 state 8 1 0 x 1 1 t state 9 1 1 x x 1 1 preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 60 lucent technologies inc. lucent technologies inc. frame formats (continued) 16-state signaling the default signaling mode while in slc -96 framing is 16-state signaling. slc -96 16-state signaling is enabled by setting both the f and g bits in the signaling registers to the 0 state, setting the slc -96 signaling control register frm_pr43 bit 3 and bit 4 to 0, and setting register frm_pr44 bit 0 to 0. table 30 shows the state of the transmit- ted signaling bits to the line as a function of the a, b, c, and d bit settings in the transmit signaling registers. in table 30 below, under transmit to the line signal bits, a and b are transmitted into one slc -96 12-frame signaling superframe, while a and b are transmitted into the next successive slc -96 12-frame signaling superframe. in the line receive direction, this signaling mode functions identically to the preceding transmit path description. the signaling mapping of this 16-state signaling mode is equivalent to the mapping of the slc -96 9-state signaling mode. table 30. 16-state signaling format transmit signaling register settings transmit to the line signal bits slc -96 signaling statesabcda bab state 0 00000000 state 1 00010001 state 2 00100010 state 3 00110011 state 4 01000100 state 5 01010101 state 6 01100110 state 7 01110111 state 8 10001000 state 9 10011001 state 10 10101010 state 11 10111011 state 12 11001100 state 13 11011101 state 14 11101110 state 15 11111111 lucent technologies inc. 61 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. frame formats (continued) cept 2.048 basic frame, crc-4 time slot 0, and signaling time slot 16 multiframe struc- tures as defined in itu rec. g.704, the cept 2.048 frame, crc-4 multiframe, and channel associated signaling multi- frame structures are illustrated in figure 24. 5-4548(f).cr.1 figure 24. itu 2.048 basic frame, crc-4 multiframe, and channel associated signaling multiframe structures 0 1 a s a4 s a5 s a6 s a7 s a8 c 1 0 0 1 1 0 1 1 c 2 0 0 1 1 0 1 1 0 1 a s a4 s a5 s a6 s a7 s a8 c 3 0 0 1 1 0 1 1 1 1 a s a4 s a5 s a6 s a7 s a8 c 4 0 0 1 1 0 1 1 0 1 a s a4 s a5 s a6 s a7 s a8 c 1 0 0 1 1 0 1 1 1 1 a s a4 s a5 s a6 s a7 s a8 c 2 0 0 1 1 0 1 1 1 1 a s a4 s a5 s a6 s a7 s a8 c 3 0 0 1 1 0 1 1 e 1 a s a4 s a5 s a6 s a7 s a8 c 4 0 0 1 1 0 1 1 e 1 a s a4 s a5 s a6 s a7 s a8 time slot 1 time slot 1 time slot 1 time slot 1 time slot 1 time slot 1 time slot 1 time slot 1 time slot 1 time slot 1 time slot 1 time slot 1 time slot 1 time slot 1 time slot 1 time slot 1 time slot 31 time slot 31 time slot 31 time slot 31 time slot 31 time slot 31 time slot 31 time slot 31 time slot 31 time slot 31 time slot 31 time slot 31 time slot 31 time slot 31 time slot 31 time slot 31 frame 0 of crc-4 multiframe time slot 0 time slot 1 time slot 16 time slot 31 si 1 a s a4 s a5 s a6 s a7 s a8 time slot 1 time slot 31 si 0 0 1 1 0 1 1 time slot 1 time slot 31 frame 15 of crc-4 multiframe fas frame not fas frame 0 0 0 0 x 0 y m x 1 x 2 12345678 8-bit time slot = 3.90625 m s 256-bit frame = 125 m s primary basic frame structure a 1 b 1 c 1 d 1 a 16 b 16 c 16 d 16 a 2 b 2 c 2 d 2 a 17 b 17 c 17 d 17 a 3 b 3 c 3 d 3 a 18 b 18 c 18 d 18 a 4 b 4 c 4 d 4 a 19 b 19 c 19 d 19 a 5 b 5 c 5 d 5 a 20 b 20 c 20 d 20 a 6 b 6 c 6 d 6 a 21 b 21 c 21 d 21 a 7 b 7 c 7 d 7 a 22 b 22 c 22 d 22 a 8 b 8 c 8 d 8 a 23 b 23 c 23 d 23 a 9 b 9 c 9 d 9 a 24 b 24 c 24 d 24 a 10 b 10 c 10 d 10 a 25 b 25 c 25 d 25 a 11 b 11 c 11 d 11 a 26 b 26 c 26 d 26 a 12 b 12 c 12 d 12 a 27 b 27 c 27 d 27 a 13 b 13 c 13 d 13 a 28 b 28 c 28 d 28 a 14 b 14 c 14 d 14 a 29 b 29 c 29 d 29 a 15 b 15 c 15 d 15 a 30 b 30 c 30 d 30 frame 0 time channel associated signaling multiframe in time slot 16 channel numbers refer to telephone channel numbers. time slots 1 to 15 and 17 to 31 are assigned to telephone channels numbered from 1 to 30. frame 15 crc-4 multiframe in time slot 0 time slot 16 multiframe slot 16 multiframe 62 lucent technologies inc. preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) october 2000 lucent technologies inc. frame formats (continued) cept 2.048 basic frame structure the itu rec. g.704 section 2.3.1 defined frame length is 256 bits, numbered 1 to 256. the frame repetition rate is 8 khz. the allocation of bits numbered 1 to 8 of the frame is shown in table 31. table 31. allocation of bits 1 to 8 of the fas frame and the not fas frame basic frames bit 1 (msb) bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 (lsb) frame alignment signal (fas) si0011011 not frame alignment signal (not fas) si 1 a sa4 sa5 sa6 sa7 sa8 the function of each bit in table 31 is described below: n the si bits are reserved for international use. a spe- cific use for these bits is described in table 32. if no use is realized, these bits should be fixed at one on digital paths crossing an international border. n bit 2 of the not fas frames is fixed to one to assist in avoiding simulations of the frame alignment signal. n bit 3 of the not fas is the remote alarm indication (a bit). in undisturbed operation, this bit is set to 0; in alarm condition, set to one. n bits 48 of the not fas (sa4sa8) may be rec- ommended by itu for use in specific point-to-point applications. bit sa4 may be used as a message- based data link for operations, maintenance, and performance monitoring. if the data link is accessed at intermediate points with consequent alterations to the sa4 bit, the crc-4 bits must be updated to retain the correct end-to-end path termination functions associated with the crc-4 procedure. the receive framer does not implement the crc-4 modifying algorithm described in tu rec. g.706 annex c. bits sa4sa8, where these are not used, should be set to one on links crossing an international border. n msb = most significant bit and is transmitted first. n lsb = least significant bit and is transmitted last. transparent framing format the transmit framer can be programmed to transpar- ently transmit 256 bits of system data to the line. the transmit framer must be programmed to either trans- parent framing mode 1 or transparent framing mode 2 (see framer reset and transparent mode control reg- ister (frm_pr26) on page 174). in transparent mode 1 or mode 2, the transmit framer transmits all 256 bits of the rchi payload unmodified to the line. time slot 1 of the rchi, determined by the rchifs signal, is inserted into the fas/notfas time slot of the transmit line interface. frame integrity is maintained in both the transmit and receive framer sections. 5-5988(f) figure 25. cept transparent frame structure in transparent framing mode 1, the receive framer is forced not to reframe on the receive line data. other than bipo- lar violations and unframed ais monitoring, there is no processing of the receive line data. the entire receive line payload is transmitted unmodified to the chi. in transparent framing mode 2, the receive framer functions normally on the receive line data. all normal monitoring of receive line data is performed and data is transmitted to the chi as programmed. time slot 1 32 time-slot chi frame time slot 2 time slot 3 time slot 31 time slot 32 time slot 1 32 time-slot line frame time slot 2 time slot 3 time slot 31 time slot 32 lucent technologies inc. 63 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. frame formats (continued) cept loss of basic frame alignment (lfa) frame alignment is assumed to be lost when: n as described in itu rec. g.706 section 4.1.1, three consecutive incorrect frame alignment signals have been received. n so as to limit the effect of spurious frame alignment signals, when bit 2 in time slot 0 in not fas frames have been received with an error on three consecu- tive occasions. n optionally, as described in itu rec. g.706 section 4.3.2, by exceeding a count of >914 errored crc-4 blocks out of 1000, with the understanding that a count of 3 915 errored crc blocks indicates false frame alignment. n on demand via the control registers. in the lfa state: n no additional fas or not fas errors are processed. n the received remote frame alarm (received a bit) is deactivated. n all not-fas bit (si bit, a bit, and sa4 to sa8 bits) processing is halted. n receive sa6 status bits are set to 0. n receive sa6 code monitoring and counting is halted. n all receive sa stack data updates are halted. the receive sa stack ready, register frm_sr4 bit 6 and bit 7, is set to 0. if enabled, the receive sa stack interrupt bit is set to 0. n receive data link (rfdl) is set to 1 and rfdclk maintains previous alignment. n optionally, the remote alarm indication (a = 1) may be automatically transmitted to the line if register frm_pr27 bit 0 is set to 1. n optionally, the alarm indication signal (ais) may be automatically transmitted to the system if register frm_pr19 bit 0 is set to 1. n if crc-4 is enabled, loss of crc-4 multiframe align- ment is forced. n if crc-4 is enabled, the monitoring and processing of crc-4 checksum errors is halted. n if crc-4 is enabled, all monitoring and processing of received e-bit information is halted. n if crc-4 is enabled, the receive continuous e-bit alarm is deactivated. n if crc-4 is enabled, optionally, e bit = 0 is transmit- ted to the line for the duration of loss of crc-4 multi- frame alignment if register frm_pr28 bit 4 is set to 1. n if time slot 16 signaling is enabled, loss of the signal- ing multiframe alignment is forced. n if time slot 16 signaling is enabled, updating of the signaling data is halted. cept loss of frame alignment recovery algorithm the receive framer begins the search for basic frame alignment one bit position beyond the position where the lfa state was detected. as defined in itu rec. g.706.4.1.2, frame alignment will be assumed to have been recovered when the following sequence is detected: n for the first time, the presence of the correct frame alignment signal in frame n . n the absence of the frame alignment signal in the fol- lowing frame detected by verifying that bit 2 of the basic frame is a 1 in frame n + 1. n for the second time, the presence of the correct frame alignment in the next frame, n + 2. failure to meet the second or third bullet above will ini- tiate a new basic frame search in frame n + 2. preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 64 lucent technologies inc. lucent technologies inc. frame formats (continued) cept time slot 0 crc-4 multiframe structure the crc-4 multiframe is in bit 1 of each not fas frame. as described in itu rec. g.704 section 2.3.3.1, where there is a need to provide additional protection against simulation of the frame alignment signal, and/or where there is a need for an enhanced error monitoring capability, then bit 1 of each frame may be used for a cyclic redundancy check-4 (crc-4) procedure as detailed below. the allocation of bits 18 of time slot 0 of every frame is shown in table 32 for the complete crc-4 multiframe. table 32. itu crc-4 multiframe structure notes: c1 to c4 = cyclic redundancy check-4 (crc-4) bits. e = crc-4 error indication bits. sa4 to sa8 = spare bits. a = remote frame alarm (rfa) bit (active-high); referred to as the a bit. the crc-4 multiframe consists of 16 frames numbered 0 to 15 and is divided into two eight-frame submultiframes (smf), designated smf-i and smf-ii that signifies their respective order of occurrence within the crc-4 multi- frame structure. the smf is the crc-4 block size (2048 bits). in those frames containing the frame alignment sig- nal (fas), bit 1 is used to transmit the crc-4 bits. there are four crc-4 bits, designated c1, c2, c3, and c4 in each smf. in those frames not containing the frame alignment signal (not fas), bit 1 is used to transmit the 6-bit crc-4 multiframe alignment signal and two crc-4 error indication bits (e). the multiframe alignment signal is defined in itu rec. g.704 section 2.3.3.4, as 001011. transmitted e bits should be set to 0 until both basic frame and crc-4 multiframe alignment are established. thereafter, the e bits should be used to indicate received errored submultiframes by setting the binary state of one e bit from 1 to 0 for each errored submultiframe. the received e bits will always be taken into account, by the receive e-bit processor * , even when the smf that contains them is found to be errored. in the case where there exists equipment that does not use the e bits, the state of the e bits should be set to a binary 1 state. * the receive e-bit processor will halt the monitoring of the received e bit during the loss of crc-4 multiframe alignment. multiframe submultiframe (smf) frame number bits 123 4 5 6 7 8 i0c10011011 1 0 1 a sa4 sa5 sa6 sa7 sa8 2 c20011011 3 0 1 a sa4 sa5 sa6 sa7 sa8 4 c30011011 5 1 1 a sa4 sa5 sa6 sa7 sa8 6 c40011011 7 0 1 a sa4 sa5 sa6 sa7 sa8 ii 8 c10011011 9 1 1 a sa4 sa5 sa6 sa7 sa8 10 c2 0 0 1 1 0 1 1 11 1 1 a sa4 sa5 sa6 sa7 sa8 12 c3 0 0 1 1 0 1 1 13 e 1 a sa4 sa5 sa6 sa7 sa8 14 c4 0 0 1 1 0 1 1 15 e 1 a sa4 sa5 sa6 sa7 sa8 lucent technologies inc. 65 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. frame formats (continued) the crc-4 word, located in submultiframe n, is the remainder after multiplication by x 4 and then division (modulo 2) by the generator polynomial x 4 + x + 1, of the polynomial representation of the submultiframe n C 1. representing the contents of the submultiframe check block as a polynomial, the first bit in the block, i.e., frame 0, bit 1 or frame 8, bit 1, is taken as being the most significant bit and the least significant bit in the check block is frame 7 or frame 15, bit 256. similarly, c 1 is defined to be the most significant bit of the remainder and c 4 the least significant bit of the remain- der. the encoding procedure, as described in itu rec. g.704 section 2.3.3.5.2, follows: n the crc-4 bits in the smf are replaced by binary zeros. n the smf is then acted upon the multiplication/divi- sion process referred to above. n the remainder resulting from the multiplication/divi- sion process is stored, ready for insertion into the respective crc-4 locations of the next smf. the decoding procedure, as described in itu rec. g.704 section 2.3.3.5.3, follows: n a received smf is acted upon by the multiplication/ division process referred to above, after having its crc-4 bits extracted and replaced by zeros. n the remainder resulting from this division process is then stored and subsequently compared on a bit-by- bit basis with the crc bits received in the next smf. n if the remainder calculated in the decoder exactly corresponds to the crc-4 bits received in the next smf, it is assumed that the checked smf is error- free. cept loss of crc-4 multiframe alignment (lts0mfa) loss of basic frame alignment forces the receive framer into a loss of crc-4 multiframe alignment state. this state is reported by way of the status registers frm_sr1 bit 2. once basic frame alignment is achieved, a new search for crc-4 multiframe align- ment is initiated. during a loss of crc-4 multiframe alignment state: n the crc-4 error counter is halted. n the crc-4 error monitoring circuit for errored sec- onds and severely errored seconds is halted. n the received e-bit counter is halted. n the received e-bit monitoring circuit for errored sec- onds and severely errored seconds at the remote end interface is halted. n receive continuous e-bit monitoring is halted. n all receive sa6 code monitoring and counting func- tions are halted. n the updating of the receive sa stack is halted and the receive sa stack interrupt is deactivated. n optionally, a = 1 may be automatically transmitted to the line if register frm_pr27 bit 2 is set to 1. n optionally, e = 0 may be automatically transmitted to the line if register frm_pr28 bit 4 is set to 1. n optionally, if lts0mfa monitoring in the perfor- mance counters is enabled, by setting registers frm_pr14 through frm_pr17 bit 1 to 1, then these counts are incremented once per second for the duration of the lts0mfa state. preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 66 lucent technologies inc. lucent technologies inc. frame formats (continued) cept loss of crc-4 multiframe alignment recovery algorithms several optional algorithms exist in the receive framer. these are selected through programming of register frm_pr9. crc-4 multiframe alignment algorithm with 8 ms timer the default algorithm is as described in itu rec. g.706 section 4.2. the recommendation states that if a condition of assumed frame alignment has been achieved, crc-4 multiframe alignment is deemed to have occurred if at least two valid crc-4 multiframe alignment signals can be located within 8 ms, the time separating two crc-4 multiframe signals being 2 ms or a multiple of 2 ms. the search for the crc-4 multi- frame alignment signal is made only in bit 1 of not fas frames. if multiframe alignment cannot be achieved within 8 ms, it is assumed that frame align- ment is due to a spurious frame alignment signal and a new parallel search for basic frame alignment is initi- ated. the new search for the basic frame alignment is started at the point just after the location of the assumed spurious frame alignment signal. during this parallel search for basic frame alignment, there is no indication to the system of a receive loss of frame align- ment (rlfa) state. during the parallel search for basic frame alignment and while in primary basic frame align- ment, data will flow through the receive framer to the system interface as defined by the current primary frame alignment. the receive framer will continuously search for crc-4 multiframe alignment. crc-4 multiframe alignment algorithm with 100 ms timer the crc-4 multiframe alignment with 100 ms timer mode is enabled by setting frm_pr9 to 0xxxx1x1 (binary). this crc-4 multiframe reframe mode starts a 100 ms timer upon detection of basic frame alignment. this is a parallel timer to the 8 ms timer. if crc-4 multi- frame alignment cannot be achieved within the time limit of 100 ms due to the crc-4 procedure not being implemented at the transmitting side, then an indication is given and actions are taken equivalent to those spec- ified for loss of basic frame alignment, namely: n optional automatic transmission of a = 0 to the line if register frm_pr27 bit 3 is set to 1. n optional automatic transmission of e = 0 to the line if register frm_pr28 bit 5 is set to 1. n optional automatic transmission of ais to the system if register frm_pr19 bit 1 is set to 1. lucent technologies inc. 67 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. frame formats (continued) 5-3909(f).er.2 figure 26. receive crc-4 multiframe search algorithm using the 100 ms internal timer ? set e bits according to itu rec. g.704, section 2.3.3.4 out of primary bfa: ? optionally disable traffic by transmitting ais to the system ? optionally transmit a = 1 and e = 0 to line ? inhibit incoming crc-4 performance monitoring bfa search? in primary bfa: ? enable traffic to the system ? transmit a = 0 and optionally e = 0 to the line ? start 8 ms and 100 ms timers ? enable primary bfa loss checking process crc-4 mfa search (itu rec. g.706, section 4.2 - note 2 ) can crc-4 mfa be found in 8 ms? parallel bfa search 100 ms timer elapsed? yes no no no yes yes assume crc-4 multiframe alignment: ? confirm primary bfa associated with crc-4 mfa ? adjust primary bfa if necessary set 100 ms timer expiration status bit to the 1 state: ? optionally transmit a bit = 1 to the line interface for the duration of lts0mfa = 1 ? optionally transmit ais to the system interface for the start crc-4 performance monitoring: ? set e bits according to itu rec. g.704, section 2.3.3.4 crc-4 count > 914 in 1 second or continue crc-4 performance monitoring: yes yes no no duration of lts0mfa = 1 is 100 ms trx = 1 ? yes no set internal 100 ms timer expiration status bit to 0: ? if transmitting a bit = 1 to the line interface, transmit a bit = 0 ? if transmitting ais to the system interface, enable data transmission to the system interface lfa = 1? good? is ? yes no 100 ms trx = 1 internal set internal 100 ms timer expiration status bit to 1: primary ? if transmitting e = 0 to the line interface, transmit e bit = 1 ? optionally transmit e bit = 0 to the line interface for the duration of ltsomfa = 1 preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 68 lucent technologies inc. lucent technologies inc. frame formats (continued) crc-4 multiframe alignment search algorithm with 400 ms timer the crc-4 multiframe alignment with 400 ms timer mode is enabled by setting frm_pr9 to 0xxx1xx1 (binary). this receive crc-4 multiframe reframe mode is the modified crc-4 multiframe alignment algorithm described in itu rec. 706 annex b, where it is referred to as crc-4-to-non-crc-4 equipment interworking. a flow diagram of this algorithm is illustrated in figure 27. when the interworking algorithm is enabled, it supersedes the 100 ms algorithm described on page 66 and in figure 26. this algorithm assumes that a valid basic frame alignment signal is consistently present but the crc-4 multiframe alignment cannot be achieved by the end of the total crc-4 multiframe alignment search period of 400 ms, if the distant end is a non-crc-4 equipment. in this mode, the following consequent actions are taken: n an indication that there is no incoming crc-4 multi- frame alignment signal. n all crc-4 processing on the receive 2.048 mbits/s signal is inhibited. n crc-4 data is transmitted to the distant end with both e bits set to zero. this algorithm allows the identification of failure of crc-4 multiframe alignment generation/detection, but with correct basic framing, when interworking between each piece of equipment having the modified crc-4 multiframe alignment algorithm. as described in itu rec. g.706 section b.2.3: n a 400 ms timer is triggered on the initial recovery of the primary basic frame alignment. n the 400 ms timer reset if and only if: the criteria for loss of basic frame alignment as described in itu rec. g.706 section 4.1.1 is achieved. if 915 out of 1000 errored crc-4 blocks are detected resulting in a loss of basic frame align- ment as described in itu rec. g.706 section 4.3.2. on-demand reframe is requested. the receive framer is programmed to the non-crc-4 mode. n the loss of basic frame alignment checking process runs continuously, irrespective of the state of the crc-4 multiframe alignment process below it. n a new search for frame alignment is initiated if crc- 4 multiframe alignment cannot be achieved in 8 ms, as described in itu rec. g.706 section 4.2. this new search for basic frame alignment will not reset the 400 ms timer or invoke consequent actions asso- ciated with loss of the primary basic frame alignment. in particular, all searches for basic frame alignment are carried out in parallel with, and independent of, the primary basic frame loss checking process. all subsequent searches for crc-4 multiframe align- ment are associated with each basic framing sequence found during the parallel search. n during the search for crc-4 multiframe alignment, traffic is allowed through, upon, and to be synchro- nized to, the initially determined primary basic frame alignment. n upon detection of the crc-4 multiframe before the 400 ms timer elapsing, the basic frame alignment associated with the crc-4 multiframe alignment replaces, if necessary, the initially determined basic frame alignment. n if crc-4 multiframe alignment is not found before the 400 ms timer elapses, it is assumed that a condi- tion of interworking between equipment with and without crc-4 capability exists and the actions described above are taken. n if the 2.048 mbits/s path is reconfigured at any time, then it is assumed that the (new) pair of path termi- nating equipment will need to re-establish the com- plete framing process, and the algorithm is reset. lucent technologies inc. 69 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. frame formats (continued) 5-3909(f).fr.3 figure 27. receive crc-4 multiframe search algorithm for automatic, crc-4/non-crc-4 equipment interworking as defined by itu (from itu rec. g.706, annex b.2.2 - 1991) ? set e bits according to itu rec. g.704, section 2.3.3.4 out of primary bfa: ? optionally disable traffic by transmitting ais to the system ? optionally transmit a bit = 1 and e bit = 0 to line ? inhibit incoming crc-4 performance monitoring bfa search? in primary bfa: ? enable traffic not transmitting ais to the system ? transmit a = 0 and optionally e = 0 to the line ? start 400 ms timer ? enable primary bfa loss checking process crc-4 mfa search (itu rec. g.706, section 4.2) can crc-4 mfa be found in 8 ms? parallel bfa search 400 ms timer elapsed? yes no no no yes yes assume crc-4-to-crc-4 interworking: ? confirm primary bfa associated with crc-4 mfa ? adjust primary bfa if necessary start crc-4 performance monitoring: ? set e bits according to itu rec. g.704, section 2.3.3.4 crc-4 count > 914 in 1 second or continue crc-4 performance monitoring: yes yes no no ? ? keep a = 0 in outgoing crc-4 data assume crc-4-to-non-crc-4 interworking: ? transmit a bit = 0 to the line interface ? stop incoming crc-4 processing ? confirm primary bfa ? transmit e bit = 0 to the line interface ? indicate no crc-4 mfa primary lfa = 1? preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 70 lucent technologies inc. lucent technologies inc. frame formats (continued) cept time slot 16 multiframe structure the T7630 supports two cept signaling modes: channel associated signaling (cas) or per-channel signaling (pcs0 and pcs1). channel associated signaling (cas) the channel associated signaling (cas) mode utilizes time slot 16 of the fas and not fas frames. the cas for- mat is a multiframe consisting of 16 frames where frame 0 of the multiframe contains the multiframe alignment pat- tern of four zeros in bits 1 through 4. table 33 illustrates the cas multiframe of time slot 16. the T7630 can be programmed to force the transmitted line cas multiframe alignment pattern to be transmitted in the fas frame by selecting the pcs0 option or in the not fas frame by selecting the pcs1 option. alignment of the transmitted line cas multiframe to the crc-4 multiframe is arbitrary. table 33. itu cept time slot 16 channel associated signaling multiframe structure notes: frame 0 bits 14 define the time slot 16 multiframe alignment. x0x2 = time slot 16 spare bits defined in frm_pr41 bit 0bit 2. y m = yellow alarm, time slot 16 remote multiframe alarm (rma) bit (1 = alarm condition). time slot 16 channel associated signaling multiframe frame number bit 12345678 00000x 0 y m x 1 x 2 1a 1 b 1 c 1 d 1 a 16 b 16 c 16 d 16 2a 2 b 2 c 2 d 2 a 17 b 17 c 17 d 17 3a 3 b 3 c 3 d 3 a 18 b 18 c 18 d 18 4a 4 b 4 c 4 d 4 a 19 b 19 c 19 d 19 5a 5 b 5 c 5 d 5 a 20 b 20 c 20 d 20 6a 6 b 6 c 6 d 6 a 21 b 21 c 21 d 21 7a 7 b 7 c 7 d 7 a 22 b 22 c 22 d 22 8a 8 b 8 c 8 d 8 a 23 b 23 c 23 d 23 9a 9 b 9 c 9 d 9 a 24 b 24 c 24 d 24 10 a 10 b 10 c 10 d 10 a 25 b 25 c 25 d 25 11 a 11 b 11 c 11 d 11 a 26 b 26 c 26 d 26 12 a 12 b 12 c 12 d 12 a 27 b 27 c 27 d 27 13 a 13 b 13 c 13 d 13 a 28 b 28 c 28 d 28 14 a 14 b 14 c 14 d 14 a 29 b 29 c 29 d 29 15 a 15 b 15 c 15 d 15 a 30 b 30 c 30 d 30 lucent technologies inc. 71 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. frame formats (continued) cept loss of time slot 16 multiframe align- ment (lts16mfa) loss of basic frame alignment forces the receive framer into a loss of time slot 16 signaling multiframe align- ment state. in addition, as defined in itu rec. g.732 section 5.2, time slot 16 signaling multiframe is assumed lost when two consecutive time slot 16 multi- frame 4-bit all-zero patterns is received with an error. also, the time slot 16 multiframe is assumed lost when, for a period of two multiframes, all bits in time slot 16 are in state 0. this state is reported by way of the sta- tus registers frm_sr1 bit 1. once basic frame align- ment is achieved, the receive framer will initiate a search for the time slot 16 multiframe alignment. during a loss of time slot 16 multiframe alignment state: n the updating of the signaling data is halted. n the received control bits forced to the binary 1 state. n the received remote multiframe alarm indication sta- tus bit is forced to the binary 0 state. n optionally, the transmit framer can transmit to the line the time slot 16 signaling remote multiframe alarm if register frm_pr41 bit 4 is set to 1. n optionally, the transmit framer can transmit the alarm indication signal (ais) in the system transmit time slot 16 data if register frm_pr44 bit 6 is set to 1. cept loss of time slot 16 multiframe align- ment recovery algorithm the time slot 16 multiframe alignment recovery algo- rithm is as described in itu rec. g.732 section 5.2. the recommendation states that if a condition of assumed frame alignment has been achieved, time slot 16 multiframe alignment is deemed to have occurred when the 4-bit time slot 16 multiframe pattern of 0000 is found in time slot 16 for the first time, and the preced- ing time slot 16 contained at least one bit in the binary 1 state. cept time slot 0 fas/not fas control bits fas/not fas si- and e-bit source the si bit can be used as an 8 kbits/s data link to and from the remote end, or in the crc-4 mode, it can be used to provide added protection against false frame alignment. the sources for the si bits that are transmit- ted to the line are the following: n cept with no crc-4 and frm_pr28 bit 0 = 1: the tsif control bit (frm_pr28 bit 1) is transmitted in bit 1 of all fas frames and the tsinf control bit (frm_pr28 bit 2) is transmitted in bit 1 of all not fas frames. n the chi system interface (cept with no crc-4 and frm_pr28 bit 0 = 0) * . this option requires the received system data (rchi- data) to maintain a biframe alignment pattern where frames containing si bit information for the not fas frames have bit 2 of time slot 0 in the binary 1 state fol- lowed by frames containing si bit information for the fas frames that have bit 2 of time slot 0 in the binary 0 state. this ensures the proper alignment of the si received system data to the transmit line si data. whenever this requirement is not met by the system, the transmit framer will enter a loss of biframe align- ment condition (indication is given in the status regis- ters) and then search for the pattern; in the loss of biframe alignment state, transmitted line data is cor- rupted (only when the system interface is sourcing sa or si data). when the transmit framer locates a new biframe alignment pattern, an indication is given in the status registers and the transmit framer resumes nor- mal operations. n cept with crc-4 ? : manual transmission of e bit = 0: if frm_pr28 bit 0 = 0, then the tsif bit (frm_pr28 bit 1) is transmitted in bit 1 of frame 13 (e bit) and the tsinf bit (frm_pr28 bit 2) is transmitted in bit 1 of frame 15 (e bit). if frm_pr28 bit 0 = 1, then each time 0 is written into tsif (frm_pr28 bit 1) one e bit = 0 is trans- mitted in frame 13, and each time 0 is written into tsinf (frm_pr28 bit 2) one e bit = 0 is transmit- ted in frame 15. * whenever bits (e.g., si, sa, etc.) are transmitted from the system transparently, frm_pr29 must first be momentarily written to 001xxxxx (binary). otherwise, the transmit framer will not be able to locate the biframe alignment. ? the receive e-bit processor will halt the monitoring of received e bits during loss of crc-4 multiframe alignment. preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 72 lucent technologies inc. lucent technologies inc. cept time slot 0 fas/not fas control bits (continued) n cept with crc-4 1 , automatic transmission of e bit = 0: optionally, one transmitted e bit is set to 0 by the transmit framer, as described in itu rec. g.704 section 2.3.3.4, for each received errored crc-4 submultiframe detected by the receive framer if frm_pr28 bit 3 = 1. optionally, as described in itu rec. g.704 sec- tion 2.3.3.4, both e bits are set to 0 while in a received loss of crc-4 multiframe alignment state 2 if frm_pr28 bit 4 = 1. optionally, when the 100 ms or 400 ms timer is enabled and the timer has expired, as described in itu rec. g.706 section b.2.2, both e bits are set to 0 for the duration of the loss of crc-4 multi- frame alignment state 2 if frm_pr28 bit 5 = 1. otherwise, the e bits are transmitted to the line in the 1 state. not fas a-bit (cept remote frame alarm) sources the a bit, as described in itu rec. g.704 section 2.3.2 table 4a/g.704, is the remote alarm indication bit. in undisturbed conditions, this bit is set to 0 and trans- mitted to the line. in the loss of frame alignment (lfa) state, this bit may be set to 1 and transmitted to the line as determined by register frm_pr27. the a bit is set to 1 and transmitted to the line for the following condi- tions: n setting the transmit a bit = 1 control bit by setting register frm_pr27 bit 7 to 1. n optionally for the following alarm conditions as selected through programming register frm_pr27. the duration of loss of basic frame alignment as described in itu rec. g.706 section 4.1.1 3 , or itu rec. g.706 section 4.3.2 4 if register frm_pr27 bit 0 = 1. the duration of loss of crc-4 multiframe align- ment if register frm_pr27 bit 2 = 1. the duration of loss of signaling time slot 16 multi- frame alignment if register frm_pr27 bit 1 = 1. the duration of loss of crc-4 multiframe align- ment after either the 100 ms or 400 ms timer expires if register frm_pr27 bit 3 = 1. the duration of receive sa6_8hex 5 if register frm_pr27 bit 4 = 1. the duration of receive sa6_chex 5 if register frm_pr27 bit 5 = 1. not fas sa-bit sources 6 the sa bits, sa4sa8, in the not fas frame can be a 4 kbits/s data link to and from the remote end. the sources and value for the sa bits are: n the sa source register frm_pr29 bit 0bit 4 if frm_pr29 bit 7bit 5 = 000 (binary) and frm_pr30 bit 4bit 0 = 11111 (binary). n the facility data link external input (tfdl) if register frm_pr29 bit 7 = 1 and register frm_pr21 bit 6 = 1. n the internal fdl-hdlc if register frm_pr29 bit 7 = 1 and register frm_pr21 bit 6 = 0. n the sa transmit stack if register frm_pr29 bit 7bit 5 are set to 01x (binary). n the chi system interface if register frm_pr29 bit 7bit 5 are set to 001 (binary). this option requires the received system data (rchidata) to maintain a biframe alignment pattern where (1) frames containing sa bit information have bit 2 of time slot 0 in the binary 1 state and (2) these not fas frames are followed by frames not containing sa bit information, the fas frames, which have bit 2 of time slot 0 in the binary 0 state. this ensures the proper alignment of the sa received system data to the transmit line sa data. whenever this requirement is not met by the system, the transmit framer will enter a loss of biframe alignment condition indicated in the status register, frm_sr1 bit 4, and then search for the pattern. in the loss of biframe align- ment state, transmitted line data is corrupted (only when the system interface is sourcing sa or si data). when the transmit framer locates a new biframe alignment pattern, an indication is given in the status registers and the transmit framer resumes normal operations. 1. the receive e-bit processor will halt the monitoring of received e bits during loss of crc-4 multiframe alignment. 2. whenever loss of frame alignment occurs, then loss of crc-4 multiframe alignment is forced. once frame alignment is estab- lished, then and only then, is the search for crc-4 multiframe alignment initiated. the receive framer unit, when programmed for crc-4, can be in a state of lfa and lts0mfa or in a state of lts0mfa only, but cannot be in a state of lfa only. 3. lfa is due to framing bit errors. 4. lfa is due to detecting 915 out of 1000 received crc-4 errored blocks. 5. see table 41 sa6 bit coding recognized by the receive framer, for a definition of this sa6 pattern. 6. whenever bits (e.g., si, sa, etc.) are transmitted from the system transparently, frm_pr29 must first be momentarily written to 001xxxxx (binary). otherwise, the transmit framer will not be able to locate the biframe alignment. lucent technologies inc. 73 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. cept time slot 0 fas/not fas control bits (continued) the receive sa data is present at: n the sa received stack, registers frm_sr54frm_sr63, if the T7630 is programmed in the sa stack mode. n the system transmit interface. the status of the received sa bits and the received sa stack is available in status register frm_sr4. the transmit and receive sa bit for the fdl can be selected by setting register frm_pr43 bit 0bit 2 as shown in table 166. sa facility data link access the data link interface may be used to source one of the sa bits. access is controlled by registers frm_pr29, frm_pr30, and frm_pr43, see not fas sa-bit sources page 72. the receive sa data is always present at the receive facility data link output pin, rfdl, along with a valid clock signal at the receive facility clock output pin, rfdlck. during a loss of frame alignment (lfa) state, the rfdl signal is forced to a 1 state while rfdlck con- tinues to toggle on the previous frame alignment. when basic frame alignment is found, rfdl is as received from the selected receive sa bit position and rfdlck is forced (if necessary) to the new alignment. the data rate for this access mode is 4 khz. the access timing for the transmit and receive facility data is illustrated in figure 28 below. during loss of receive clock (lofrmrlck), rfdl and rfdlck are frozen in a state at the point of the lofrmrlck being asserted. 5-3910(f).dr.1 figure 28. facility data link access timing of the transmit and receive framer sections in the cept mode t8 t9 t9 t10 t11 t8: tfdlck cycle = 250 m s t9: tfdl to tfdlck setup/hold = 40 ns t10: rfdlck cycle = 250 m s t11: rfdlck to rfdl delay = 40 ns tfdlck tfdl rfdlck rfdl preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 74 lucent technologies inc. lucent technologies inc. cept time slot 0 fas/not fas control bits (continued) not fas sa stack source and destination the transmit sa4 to sa8 bits may be sourced from the transmit sa stack, registers frm_pr31frm_pr40. the sa stack consists of ten 8-bit registers that contain 16 not fas frames of sa information as shown in table 34. the transmit stack data may be transmitted either in non-crc-4 mode or in crc-4 mode to the line. the receive stack data, registers frm_sr54frm_sr63, is valid in both the non-crc-4 mode and the crc-4 mode. in the non-crc-4 mode while in the loss of frame alignment (lfa) state, updating of the receive sa stack is halted and the transmit and receive stack interrupts are deactivated. in the crc-4 mode while in the loss of time slot 0 multiframe alignment (lts0mfa) state, updating of the receive sa stack is halted and the transmit and receive stack interrupts are deactivated. table 34. transmit and receive sa stack structure the most significant bit of the first byte is transmitted to the line in frame 1 of a double crc-4 multiframe. the least significant bit of the second byte is transmitted to the line in frame 31 of the double crc-4 multiframe. the protocol for accessing the sa stack information for the transmit and receive sa4 to sa8 bits is shown in figure 29 and described briefly below. the device indicates that it is ready for an update of its transmit stack by setting register frm_sr4 bit 7 (cept transmit sa stack ready) high. at this time, the system has about 4 ms to update the stack. data written to the stack during this interval will be transmitted during the next double crc-4 multiframe. by reading register frm_sr4 bit 7, the system clears this bit so that it can indicate the next time the transmit stack is ready. if the transmit stack is not updated, then the content of the stack is retransmitted to the line. the 32-frame interval of the transmit framer in the non-crc-4 mode is arbitrary. enabling transmit crc-4 mode forces the updating of the internal transmit stack at the end of the 32-frame crc-4 double multiframe; the transmit sa stack is then transmitted synchronous to the transmit crc-4 multiframe structure. on the receive side, the T7630 indicates that it has received data in the receive sa stack, register frm_sr54 frm_sr63, by setting register frm_sr4 bit 6 (cept receive sa stack ready) high. the system then has about 4 ms to read the contents of the stack before it is updated again (old data lost). by reading register frm_sr4 bit 6, the system clears this bit so that it can indicate the next time the receive stack is ready. the receive framer always updates the content of the receive stack so unread data will be overwritten. the last 16 valid sa4 to sa8 bits are always stored in the receive sa stack on a double-multiframe boundary. the 32-frame interval of the receive framer in the non-crc-4 mode is arbitrary. enabling the receive crc-4 mode forces updating of the receive sa stack at the end of the 32-frame crc-4 double multiframe. the receive sa stack is received synchronous to the crc-4 multiframe structure. register number bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) 1 sa4-1 sa4-3 sa4-5 sa4-7 sa4-9 sa4-11 sa4-13 sa4-15 2 sa4-17 sa4-19 sa4-21 sa4-23 sa4-25 sa4-27 sa4-29 sa4-31 3 sa5-1 sa5-3 sa5-5 sa5-7 sa5-9 sa5-11 sa5-13 sa5-15 4 sa5-17 sa5-19 sa5-21 sa5-23 sa5-25 sa5-27 sa5-29 sa5-31 5 sa6-1 sa6-3 sa6-5 sa6-7 sa6-9 sa6-11 sa6-13 sa6-15 6 sa6-17 sa6-19 sa6-21 sa6-23 sa6-25 sa6-27 sa6-29 sa6-31 7 sa7-1 sa7-3 sa7-5 sa7-7 sa7-9 sa7-11 sa7-13 sa7-15 8 sa7-17 sa7-19 sa7-21 sa7-23 sa7-25 sa7-27 sa7-29 sa7-31 9 sa8-1 sa8-3 sa8-5 sa8-7 sa8-9 sa8-11 sa8-13 sa8-15 10 sa8-17 sa8-19 sa8-21 sa8-23 sa8-25 sa8-27 sa8-29 sa8-31 lucent technologies inc. 75 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. cept time slot 0 fas/not fas control bits (continued) 5-3911(f).c figure 29. transmit and receive sa stack accessing protocol system access sa stack (sass) interval: transmit framer unit transmits to the line the data in the transmit sa stack written during the previous sass interval. the system can update the transmit sa stack registers for transmission in the next crc-4 double multiframe. the system can read the receive sa stack registers to access the sa bits extracted during the previous valid (in multiframe alignment) double crc-4 multiframe. start of crc-4 double multiframe: ? basic frame alignment found, or, ? crc-4 multiframe alignment found. 1) 2) 3) 31 frames system access sa stack interval crc-4 double multiframe start frame 1 of 32 in dmf. internal sa stack update interval 31 frames 1-frame interval crc-4 double multiframe: 32 frames system access is disabled during this interval: the internal transmit sa stack is updated from the framer units 10-byte transmit stack control registers during this 1-frame interval. access to the stack control registers is disabled during this 1-frame interval. 1) 2) once loaded, the information in the internal transmit sa stack is transmitted to the line during the next crc-4 double multiframe, aligned to the crc-4 multiframe. if the transmit sa stack is not updated, then the content of the transmit sa stacks is retransmitted to the line. the system read-only receive stack is updated from the internal receive stack information registers. in non-crc-4 mode, the receive sa stack extracting circuitry assumes an arbitrary double 16-frame multiframe structure (32 frames), and data is extracted only in the frame aligned state. in crc-4 mode, the receive sa stack information is aligned to a crc-4 double multiframe structure (32 frames), and the data is extracted only in crc-4 multiframe aligned state. 1 frame 3) 4) 5) 6) 7) (dmf): 32 frames preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 76 lucent technologies inc. lucent technologies inc. cept time slot 0 fas/not fas control bits (continued) interrupts indicating the transmit sa stack or the receive sa stack are ready for system access are avail- able, see register frm_sr4 bit 6 and bit 7. cept time slot 16 x0x2 control bits each of the three x bits in frame 0 of the time slot 16 multiframe can be used as a 0.5 kbits/s data link to and from the remote end. the transmitted line x bits are sourced from control register frm_pr41 bit 0bit 2. in the loss of ts16 multiframe alignment (lts16mfa) state, receive x bits are set to 1 in status register frm_sr53. signaling access signaling information can be accessed by three differ- ent methods: transparently through the chi, via the control registers, or via the chi associated signaling mode. transparent signaling this mode is enabled by setting register frm_pr44 bit 0 to 1. data at the received rchidata interface passes through the framer undisturbed. the framer generates an arbitrary signaling multiframe in the transmit and receive directions to facilitate the access of signaling information at the system interface. ds1: robbed-bit signaling microprocessor control registers to enable signaling, register frm_pr44 bit 0 must be set to 0 (default). the information written into the f and g bits of the transmit signaling registers, frm_tsr0 frm_tsr23, defines the robbed-bit signaling mode for each channel for both the transmit and receive direc- tions. the per-channel programming allows the system to combine voice channels with data channels within the same frame. the receive-channel robbed-bit signaling mode is always defined by the state of the f and g bits in the corresponding transmit signaling registers for that channel. the received signaling data is stored in the receive signaling registers, frm_rsr0 frm_rsr23, while receive framer is in both the frame and superframe alignment states. updating the receive signaling registers can be inhibited on-demand, by set- ting register frm_pr44 bit 3 to 1, or automatically when either a framing error event, a loss of frame, or superframe alignment state is detected or a controlled slip event occurs. the signaling inhibit state is valid for at least 32 frames after any one of the following: a framing errored event, a loss of frame and/or super- frame alignment state, or a controlled slip event. in the common channel signaling mode, data written in the transmit signaling registers is transmitted in chan- nel 24 of the transmit line bit stream. the f and g bits are ignored in this mode. the received signaling data from channel 24 is stored in receive signaling registers frm_rsr0frm_rsr23 for t1. associated signaling mode this mode is enabled by setting register frm_pr44 bit 2 to 1. signaling information in the associated signaling mode (asm) is allocated an 8-bit system time slot in conjunc- tion with the pay load data information for a particular channel. the default system data rate in the asm mode is 4.096 mbits/s. each system channel consists of an 8-bit payload time slot followed by its correspond- ing 8-bit signaling time slot. the format of the signaling byte is identical to that of the signaling registers. in the asm mode, writing the transmit signaling regis- ters will corrupt the transmit signaling data. in the trans- mit signaling register asm (tsr-asm) format, enabled by setting register frm_pr44 bit 2 and bit 5 to 1, the system must write into the f and g bit 1 of the transmit signaling registers to program the robbed-bit signaling state mode of each ds0. the abcd bits are sourced from the rchi ports when tsr-asm mode is enabled. 1. all other bits in the signaling registers are ignored, while the f and g bits in the received rchidata stream are ignored. lucent technologies inc. 77 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. signaling access (continued) table 35 illustrates the asm time-slot format for valid channels. table 35. associated signaling mode chi 2-byte time-slot format for ds1 frames * x indicates bits that are undefined by the framer. ? the identical sense of the received system p bit in the transmitted signaling data is echoed back to the system in the received signaling information. the ds1 framing formats require rate adaptation from the line-interface 1.544 mbits/s bit stream to the system- interface 4.096 mbits/s bit stream. the rate adaptation results in the need for stuffed time slots on the system inter- face. table 36 illustrates the asm format for t1 stuffed channels used by the T7630. the stuffed data byte contains the programmable idle code in register frm_pr23 (default = 7f (hex)), while the signaling byte is ignored. table 36. associated signaling mode chi 2-byte time-slot format for stuffed channels * x indicates bits which are undefined by the framer. cept: time slot 16 signaling microprocessor control registers to enable signaling, register frm_pr44 bit 0 must be set to 0 (default). the information written into transmit signaling control registers frm_tsr0frm_tsr31 define the state of the abcd bits of time slot 16 transmitted to the line. the received signaling data from time slot 16 is stored in receive signaling registers frm_rsr0frm_rsr31. associated signaling mode signaling information in the associated signaling mode (asm), register frm_pr44 bit 2 = 1, is allocated an 8-bit system time slot in conjunction with the data information for a particular channel. the default system data rate in the asm mode is 4.096 mbits/s. each system channel consists of an 8-bit payload time slot followed by its associ- ated 8-bit signaling time slot. the format of the signaling byte is identical to the signaling registers. table 37 illustrates the asm time-slot format for valid cept e1 time slots. table 37. associated signaling mode chi 2-byte time-slot format for cept * in the cept formats, these bits are undefined. ? the p bit is the parity-sense bit calculated over the 8 data bits, the abcd (and e) bits, and the p bit. the identical sense of the received system p bit in the transmitted signaling data is echoed back to the system in the received signaling information. ds1: asm chi time slot payload data signaling information* 12345678abcdxfgp ? asm chi time slot payload data signaling information* 01 1 1 1 1 1 1xxxxxxxx cept asm chi time slot payload data signaling information 12345678abcdex * x * p ? preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 78 lucent technologies inc. lucent technologies inc. auxiliary framer i/o timing transmit and receive clock and data signals are provided by terminals rfrmck (receive framer clock), rfrm- data (receive framer data), rfs (receive frame sync), rssfs (receive framer signaling superframe sync), rcrc- mfs (receive frame crc-4 multiframe sync), tfs (transmit framer frame sync), tssfs (transmit framer signaling superframe sync), and tcrcmfs (transmit framer crc-4 multiframe sync). the receive signals are synchronized to the internal recovered receive line clock, rfrmck, and the transmit sig- nals are synchronized to the transmit line clock, tlck. note that tlck is derived from the external pllck which must be phase-locked to the system (chi) clock, rchick, see table 1, pin 7 and pin 31. detailed timing specifications for these signals are given in figure 30figure 37. 5-6290(f)r.5 figure 30. timing specification for rfrmck, rfrmdata, and rfs in ds1 mode 5-6292(f)r.6 figure 31. timing specification for tfs, tlck, and tpd in ds1 mode rfrmck rfs rfrmdata time slot 1 time slot 24 bit 7 bit 1 data valid bit 0 125 m s tlck tfs tpd ts1 125 m s ts1 (single rail) ts2 ts24 f bit bit 0 (msb) f bit bit 0 (msb) lucent technologies inc. 79 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) lucent technologies inc. auxiliary framer i/o timing (continued) 5-6294(f)r.5 figure 32. timing specification for rfrmck, rfrmdata, and rfs in cept mode 5-6295(f)r.7 figure 33. timing specification for rfrmck, rfrmdata, rfs, and rssfs in cept mode rfrmck rfs rfrmdata fas/nfas: time slot 0 time slot 31 bit 7 bit 1 data valid bit 0 125 m s rfrmck rfs rssfs rfrmdata ts0 of the frame after the frame containing the 2 ms signaling multiframe pattern (0000) ts0 of the frame after the frame containing the signaling multiframe pattern (0000) 125 m s preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 80 lucent technologies inc. lucent technologies inc. auxiliary framer i/o timing (continued) 5-6296(f)r.5 figure 34. timing specification for rcrcmfs in cept mode 5-6297(f)r.5 figure 35. timing specification for tfs, tlck, and tpd in cept mode 5-6298(f)r.5 figure 36. timing specification for tfs, tlck, tpd, and tssfs in cept mode rfrmclk rfs rcrcmfs rfrmdata ts0 of frame #0 of multiframe ts0 of frame #0 of multiframe 2 ms tlck tfs tpd ts0 of frame x 125 m s ts0 of frame x + 1 (single rail) tfs tlck tssfs tpd (single ts0 of the frame 2 ms 11 clock cycles containing the signaling multiframe pattern (0000) rail) lucent technologies inc. 81 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) lucent technologies inc. auxiliary framer i/o timing (continued) 5-6299(f)r.5 figure 37. timing specification for tfs, tlck, tpd, and tcrcmfs in cept mode alarms and performance monitoring interrupt generation a global interrupt (pin 99) may be generated if enabled by register greg1. this interrupt is clocked using channel 1 framer receive line clock (rlck1). if rlck1 is absent, the interrupt is clocked using rlck2, the receive line clock of channel 2. if both rlck1 and rlck2 are absent, clocking of interrupts is controlled by an interval 2.048 mhz clock generated from the chi clock. timing of the interrupt is shown in figure 38 there is no relation between mpck (pin 101) and the interrupt, i.e., mpck maybe asynchronous with any of the other terminator clocks. 5-6563(f) figure 38. relation between rlck1 and interrupt (pin 99) tlck tfs t crcmfs tpd (single ts0 of frame #8 1 ms of multiframe rail) ts0 of frame #0 of multiframe ts0 of frame #0 of multiframe 1 ms rlck1 interrupt (pin 99) alarm definition the receive framer monitors the receive line data for alarm conditions and errored events, and then presents this information to the system through the microproces- sor interface status registers. the transmit framer, to a lesser degree, monitors the receive system data and presents the information to the system through the microprocessor interface status registers. updating of the status registers is controlled by the receive line clock signal. when the receive loss of clock monitor determines that the receive line clock signal is lost, the system clock is used to clock the status registers and all status information should be considered corrupted. although the precise method of detecting or generating alarm and error signals differs between framing modes, the functions are essentially the same. the alarm con- ditions monitored on the received line interface are the following: 1. red alarm or the loss of frame alignment indica- tion (frm_sr1 bit 0). the red alarm indicates that the receive frame align- ment for the line has been lost and the data cannot be properly extracted. the red alarm is indicated by the loss of frame condition for the various framing formats as defined in table 38. preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 82 lucent technologies inc. lucent technologies inc. alarms and performance monitoring (continued) table 38. red alarm or loss of frame alignment conditions 2. yellow alarm or the remote frame alarm (frm_sr1 bit 0). this alarm is an indication that the line remote end is in a loss of frame alignment state. indication of remote frame alarm (commonly referred to as a yellow alarm) as for the different framing formats is shown in table 39. table 39. remote frame alarm conditions 3. blue alarm or the alarm indication signal (ais). the alarm indication signal (ais), sometimes referred to as the blue alarm, is an indication that the remote end is out of service. detection of an incoming alarm indication signal is defined in table 40. table 40. alarm indication signal conditions framing format number of errored framing bits that will cause a red alarm (loss of frame alignment) condition d4 2 errored frame bits (f t or f s ) out of 4 consecutive frame bits if frm_pr10 bit 2 = 1. 2 errored f t bits out of 4 consecutive f t bits if prm_pr10 bit 2 = 0. slc -96 2 errored frame bits (f t or f s ) out of 4 consecutive frame bits if frm_pr10 bit 2 = 1. 2 errored f t bits out of 4 consecutive f t bits if frm_pr10 bit 2 = 0. dds: frame 3 errored frame bits (f t or f s ) or channel 24 fas pattern out of 12 consecutive frame bits. esf 2 errored f e bits out of 4 consecutive f e bits or, optionally, 320 or more crc6 errored checksums within a one second interval if loss of frame alignment due to excessive crc-6 errors is enabled in frm_pr9. cept three consecutive incorrect fas patterns or three consecutive incorrect not fas patterns; or optionally, greater than 914 received crc-4 checksum errors in a one second interval if loss of frame alignment due to excessive crc-6 errors is enabled in frm_pr9. framing format remote frame alarm format superframe: d4 bit 2 of all time slots in the 0 state. superframe: d4-japanese the twelfth framing bit in the 1 state in two out of three consecutive superframes. superframe: dds bit 6 of time slot 24 in the 0 state. extended superframe (esf) an alternating pattern of eight ones followed by eight zeros in the esf data link. cept: basic frame bit 3 of the not fas frame in the 1 state in three consecutive frames. cept: signaling multiframe bit 6 of the time slot 16 signaling frame in the 1 state. framing format remote frame alarm format t1 loss of frame alignment occurs and the incoming signal has two or fewer zeros in each of two consecutive double frame periods (386 bits). cept etsi as described in ets 300 233:1994 section 8.2.2.4, loss of frame alignment occurs and the framer receives a 512 bit period containing two or less binary zeros. this is enabled by setting register frm_pr10 bit 1 to 0. cept itu as described in itu rec. g.775, the incoming signal has two or fewer zeros in each of two consecutive double frame periods (512 bits). ais is cleared if each of two consecutive double frame periods contains three or more zeros or frame alignment signal (fas) has been found. this is enabled by setting register frm_pr10 bit 1 to 1. lucent technologies inc. 83 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. alarms and performance monitoring (continued) 4. the slip condition (frm_sr3 bit 6 and bit 7). slip is defined as the state in which the receive elastic store buffers write address pointer from the receive framer and the read address pointer from the transmit chi are equal * . n the ne g ative slip ( slip-n ) alarm indicates that the receive line clock ( rlck ) - transmit chi clock ( tchick ) mon- itorin g circuit detects a state of overflow caused b y rlck and tchick bein g out of phase-lock and the period of the received frame bein g less than that of the s y stem frame. one s y stem frame is deleted. n the positive slip ( slip-p ) alarm indicates the line clock ( rlck ) - transmit chi clock ( tchick ) monitorin g circuit detects a state of underflow caused b y rlck and tchick bein g out of phase-lock and the period of the received frame bein g g reater than that of the s y stem frame. one s y stem frame is repeated. 5. the loss of framer receive clock (lofrmrlck, pins 2 and 38). in the framer mode, framer = 0 (pin 41/141), lofrmrlck alarm is asserted high when an interval of 250 s has expired with no transition of rlck (pin 135/47) detected. the alarm is disabled on the first transition of rlck. in the terminator mode, framer = 1 (pin 41/141), lofrmrlck is asserted high when sysck (pin 3/35) does not toggle for 250 s. the alarm is disabled on the first transition of sysck. 6. the loss of pll clock (lopllck, pins 39 and 143). lopllck alarm is asserted high when an interval of 250 s has expired with no transition of pllck detected. the alarm is disabled 250 s after the first transition of pllck. timing for lopllck is shown in figure 39. 5-6564(f)r.2 figure 39. timing for generation of lopllck (pin 39/143) 7. received bipolar violation errors alarm, frm_sr3 bit 0. this alarm indicates any bipolar decoding error or detection of excessive zeros. 8. received excessive crc errors alarm, frm_sr3 bit 3. in esf, this alarm is asserted when 320 or more crc-6 checksum errors are detected within a one second inter- val. in cept, this alarm is asserted when 915 or more crc-4 checksum errors are detected within a one second interval. * after a reset, the read and write pointers of the receive path elastic store will be set to a known state. pllck lopllck rchick 250 m s 250 m s preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 84 lucent technologies inc. lucent technologies inc. alarms and performance monitoring (continued) 9. the cept continuous e-bit alarm (crebit) (frm_sr2 bit 2). n crebit is asserted when the receive framer detects: five consecutive seconds where each 1 second interval contains 3 991 received e bits = 0 events. simultaneously no lfa occurred. optionally, no remote frame alarm (a bit = 1) was detected if register frm_pr9 bit 0, bit 4, and bit 5 are set to 1. optionally, neither sa6-f hex nor sa6-e hex codes were detected if register frm_pr9 bit 0, bit 4, and bit 6 are set to 1. the five second timer is started when: crc-4 multiframe alignment is achieved. and optionally, a = 0 is detected if register frm_pr9 bit 0, bit 4, and bit 5 are set to 1. and optionally, neither sa6 _ f hex 1 nor sa6 _ e hex * is detected if register frm_pr9 bit 0, bit 4, and bit 6 are set to 1. n the five second counter is restarted when: lfa occurs, or e990 e bit = 0 events occur in 1 second, or optionally, an a bit = 1 is detected if register frm_pr9 bit 0, bit 4, and bit 5 are set to 1. optionally, a valid sa6 pattern 1111 (binary) or sa6 pattern 1110 (binary) code was detected if register frm_pr9 bit 0, bit 4, and bit 6 are set to 1. this alarm is disabled during loss of frame alignment (lfa) or loss of crc-4 multiframe alignment (lts0mfa). 10. failed state alarm or the unavailable state alarm, frm_sr5 bit 3 and bit 7 and frm_sr6 bit 3 and bit 7. this alarm is defined as the unavailable state at the onset of ten consecutive severely errored seconds. in this state, the receive framer inhibits incrementing of the severely errored and errored second counters for the duration of the unavailable state. the receive framer deasserts the unavailable state condition at the onset of ten consecutive errored seconds which were not severely errored. 11. the 4-bit sa6 codes (frm_sr2 bit 3bit 7). sa6 codes are asserted if three consecutive 4-bit pat- terns have been detected. the alarms are disabled when three consecutive 4-bit sa6 codes have been detected that are different from the pattern previously detected. the receive framer monitors the sa6 bits for special codes described in ets draft prets 300 233:1992 section 9.2. the sa6 codes are defined in tables 41 and 42. the sa6 codes in table 41 may be recognized as an asynchronous bit stream in either non-crc-4 or crc-4 modes as long as the receive framer is in the basic frame alignment state. in the crc-4 mode, the receive framer can optionally recog- nize the received sa6 codes in table 41 synchronously to the crc-4 submultiframe structure as long as the receive framer is in the crc-4 multiframe alignment state (synchronous sa6 monitoring can be enabled by setting register frm_pr10 bit 1 to 1). the sa6 codes in table 42 are only recognized synchronously to the crc-4 submultiframe and when the receive framer is in crc-4 multiframe alignment. the detection of three (3) consecutive 4-bit patterns are required to indicate a valid received sa6 code. the detection of sa6 codes is indicated in status register frm_sr2 bit 3bit 7. once set, any three-nibble (12-bit) interval that con- tains any other sa6 code will clear the current sa6 sta- tus bit. interrupts may be generated by the sa6 codes given in table 41. table 41. sa6 bit coding recognized by the receive framer-asynchronous bit stream * see table 41, sa6 bit coding recognized by the receive framer, for a definition of this sa6 pattern. code first receive bit (msb) last received bit (lsb) sa6_8 hex 100 0 sa6_a hex 101 0 sa6_c hex 110 0 sa6_e hex 111 0 sa6_f hex 111 1 lucent technologies inc. 85 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) lucent technologies inc. alarms and performance monitoring (continued) table 42 defines the three 4-bit sa6 codes that are always detected synchronously to the crc-4 submultiframe structure and are only used for counting nt1 events. table 42. sa6 bit coding recognized by the receive frame-synchronous bit stream the reference points for receive crc-4, e bit, and sa6 decoding are illustrated in figure 40. 5-3913(f)r.8 figure 40. the t and v reference points for a typical cept e1 application 12. cept auxiliary pattern alarm (auxp) (frm_sr1 bit 6). the received auxiliary alarm, register frm_sr1 bit 6 (auxp), is asserted when the receive framer is in the lfa state and has detected more than 253 10 (binary) patterns for 512 consecutive bits. in a 512-bit interval, only two 10 (binary) patterns are allowable for the alarm to be asserted and maintained. the 512-bit interval is a sliding win- dow determined by the first 10 (binary) pattern detected. this alarm is disabled when three or more 10 (binary) pat- terns are detected in 512 consecutive bits. the search for auxp is synchronized with the first alternating 10 (binary) pattern as shown in table 43. table 43. auxp synchronization and clear sychronization process code first receive bit (msb) last received bit (lsb) event at nt1 counter size (bits) sa6_1 hex 000 1 e = 0 16 sa6_2 hex 0 0 1 0 crc-4 error 16 sa6_3 hex 0 0 1 1 crc-4 error & e = 0 this code will cause both counters to increment. 00 10 10 01 11 11 00 00 0 10 00 10 sync clear sync sync . . . . . . nt2 e bit = 0 nt1 et v reference e bit = 0, error event detected at the nt1 remote crc-4 errors at the nt1 e bit = 0, error event at the et remote crc-4 errors at the et, crc-4 errors detected from nt1 remote, then set sa6 = 001x e = 0 detected from nt1 remote, then set sa6 = 00x1 point t reference point count: 1) crc errors, 2) e = 0, 3) sa6 = 001x, and 4) sa6 = 00x1 sa6 crc error detected crc error detected (nt1 remote) e bit = 0 preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 86 lucent technologies inc. lucent technologies inc. alarms and performance monitoring (continued) event counters definition the error events monitored in the receive framers status registers are defined in table 44 for the hardwired (default) threshold values. the errored second and severely errored second threshold registers can be pro- grammed through frm_pr11frm_pr13 such that the errored and severely errored second counters function as required by system needs. ds1 errors are reported in the et error registers, frm_sr20 through frm_sr35. for the framer to correctly report coding and bpv errors, the liu/framer interface must ber configured as dual-rail mode. table 44. event counters definition error event functional mode definition counter size (bits) bipolar violations (bpvs) ami any bipolar violation or 16 or more consecutive zeros. 16 b8zs any bpv, code violation, or any 8-bit interval with no one pulse. cept hdb3 any bpv, code violation, or any 4-bit interval with no one pulse. frame alignment errors (fers) sf: d4 any f t or f s bit errors (frm_pr10 bit 2 = 1) or any f t bit errors (frm_pr10 bit 2 = 0). 16 sf: slc -96 any f t or f s bit errors (frm_pr10 bit 2 = 1) or any f t bit errors (frm_pr10 bit 2 = 0). sf: dds any f t , f s , or time slot 24 fas bit error. esf any f e bit error. cept any fas (0011011) or not fas (bit 2) bit error. crc checksum errors esf or cept with crc any received checksum in error. 16 excessive crc errors esf 3 320 checksum errors in a one second interval. none cept with crc 3 915 checksum errors in a one second interval. received e bits = 0 cept with crc-4 e bits = 0 in frame 13 and frame 15. 16 errored second events all any one of the relevant error conditions enabled in reg- isters frm_pr14frm_pr18 within a one second interval. 16 ds1: non esf any framing bit errors within a one second interval. ds1: esf any crc-6 errors within a one second interval. cept without crc-4 any framing errors within a one second interval. cept with crc-4 (et1) any crc-4 errors within a one second interval. cept with crc-4 (et1 remote) any e bit = 0 event within a one second interval. cept with crc-4 (nt1) any sa6 = 001x (binary) code event within a one sec- ond interval. cept with crc-4 (nt1 remote) any sa6 = 00x1 (binary) code event within a one sec- ond interval. lucent technologies inc. 87 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. alarms and performance monitoring (continued) table 44 . event counters definition (continued) the receive framer enters an unavailable state condition at the onset of ten consecutive severely errored second events. when in the unavailable state, the receive framer deasserts the unavailable state alarms at the onset of ten consecutive seconds which were not severely errored. error event functional mode definition counter size (bits) bursty errored second events ds1: non esf greater than 1 but less than 8 framing bit errors within a one second interval. 16 ds1: esf greater than 1 but less than 320 crc-6 errors within a one second interval. cept without crc-4 greater than 1 but less than 16 framing bit errors within a one second interval. cept with crc-4 (et1) greater than 1 but less than 915 crc-4 errors within a one second interval. cept with crc-4 (et1 remote) greater than 1 but less than 915 e bit = 0 events within a one second interval. cept with crc-4 (nt1) greater than 1 but less than 915 sa6 = 001x (binary) code events within a one second interval. cept with crc-4 (nt1 remote) greater than 1 but less than 915 sa6 = 00x1 (binary) code events within a one second interval. severely errored second events all any one of the relevant error conditions enabled in registers frm_pr14frm_pr18 within a one sec- ond interval. 16 ds1: non esf 8 or more framing bit errors within a one second interval. ds1: esf 320 or more crc-6 errors within a one second inter- val. cept with no crc-4 16 or more framing bit errors within a one second interval. cept with crc-4 (et1) 915 or more crc-4 errors within a one second inter- val. cept with crc-4 (et1 remote) 915 or more e bit = 0 events within a one second interval. cept with crc-4 (nt1) 915 or more sa6 = 001x (binary) code events within a one second interval. cept with crc-4 (nt1 remote) 915 or more sa6 = 00x1 (binary) code events within a one second interval. unavailable sec- ond events all a one second period in the unavailable state. 16 preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 88 lucent technologies inc. lucent technologies inc. alarms and performance monitoring (continued) loopback and transmission modes primary loopback modes framer primary loopback mode is controlled by register frm_pr24. there are seven primary loopback and transmission test modes supported: n line loopback (llb). n board loopback (blb). n single time-slot system loopback (stsslb). n single time-slot line loopback (stsllb). n cept nailed-up broadcast transmission (cnubt). n payload loopback (pllb). n cept nailed-up connect loopback (cnuclb). the loopback and transmission modes are described in detail below: n the llb mode loops the receive line data and clock back to the transmit line. the received data is pro- cessed by the receive framer and transmitted to the system interface. this mode can be selected by set- ting register frm_pr24 to 001xxxxx (binary). n the blb mode loops the receive system data back to the system after: the transmit framer processes the data, and the receive framer processes the data. in the blb mode, ais is always transmitted to the line interface. this mode can be selected by set- ting register frm_pr24 to 010xxxxx (binary). n the stsslb mode loops one and only one received system time slot back to the transmit system inter- face. the selected looped back time-slot data is not processed by either the transmit framer or the receive framer. the selected time slot does not pass through the receive elastic store buffer and therefore will not be affected by system-ais, rlfa conditions, or controlled slips events. once selected, the desired time-slot position has the programmable idle code in register frm_pr22 transmitted to the line interface one frame before implementing the loopback and for the duration of the loopback. this mode can be selected by setting register frm_pr24 to 011a 4 a 3 a 2 a 1 a 0 , where a 4 a 3 a 2 a 1 a 0 is the binary address of the selected time slot. n the stsllb mode loops one and only one received line time slot back to the transmit line. the selected time-slot data is looped to the line after being pro- cessed by the receive framer, and it passes through the receive elastic store. the selected time slot has the programmable idle code in register frm_pr22 transmitted to the system interface one frame before implementing the loopback and for the duration of the loopback. in cept, selecting time slot 0 has the effect of deactivating the current loopback mode while no other action will be taken (time slot 0 will not be looped back to the line and should not be cho- sen). this mode can be selected by setting register frm_pr24 to 100a 4 a 3 a 2 a 1 a 0 , where a 4 a 3 a 2 a 1 a 0 is the binary address of the selected time slot. n the cnubt mode transmits received-line time slot x to the system in time slots x and time slot 0 (of the next frame). any time slot can be broadcast. this mode can be selected by setting register frm_pr24 to 101a 4 a 3 a 2 a 1 a 0 where a 4 a 3 a 2 a 1 a 0 is the binary address of the selected time slot. n the pllb mode loops the received line data and clock back to the transmit line while inserting (replac- ing) the facility data link in the looped back data. two variations of the payload loopback are available. in the pass through framing/crc bit mode (chosen by setting register frm_pr24 to 111xxxxx (binary)), the framing and crc bits are looped back to the line transmit data. in the regenerated framing/crc bit mode (chosen by setting register frm_pr24 to 110xxxxx (binary) and register frm_pr10 bit 3 to 0), the framing and crc bits are regenerated by the transmit framer. the payload loopback is only avail- able for esf and cept modes. n the cnuclb mode loops received system time slot x back to the system in time slot 0. the selected time slot is not routed through the receive elastic store buffer and therefore will not be affected by system- ais, rlfa conditions, or controlled slips. any time slot can be looped back to the system. time slot x transmitted to the line is not affected by this loopback mode. looping received system time slot 0 has no effect on time slot 0 transmitted to the line, i.e., the transmit framer will always overwrite the fas and not fas data in time slot 0 transmitted to the line. this mode can be selected by setting register frm_pr24 to 110a 4 a 3 a 2 a 1 a 0 and register frm_pr10 bit 3 to 1, where a 4 a 3 a 2 a 1 a 0 is the binary address of the selected time slot. lucent technologies inc. 89 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. alarms and performance monitoring (continued) secondary loopback modes there are two secondary loopback modes supported: n secondary-single time-slot system loopback (s-stsslb) n secondary-single time-slot line loopback (s-stsllb) the loopbacks are described in detail below: n the secondary-stsslb mode loops one and only one received system time slot back to the transmit system interface. the selected time-slot data looped back is not processed by either the transmit framer or the receive framer. the selected time slot does not pass through the receive elastic store buffer and therefore will not be affected by system-ais, rlfa conditions, or controlled slips events. whenever the secondary loopback register is programmed to the same time slot as the primary register, the primary loopback mode will control that time slot. once selected, the desired time-slot position has the pro- grammable line idle code in register frm_pr22 transmitted to the line interface one frame before implementing the loopback and for the duration of the loopback. n the secondary-stsllb mode loops one and only one line time slot back to the line. the selected time slot data is looped to the line after being processed by the receive framer and it passes through the receive elastic store. the selected time slot has the programmable idle code in register frm_pr22 transmitted to the system interface one frame before implementing the loopback and for the duration of the loopback. in cept, selecting time slot 0 has the effect of deactivating the current loopback mode while no other action will be taken (time slot 0 will not be looped back to the line and should not be chosen in this mode). table 45 defines the deactivation of the two secondary loopback modes as a function of the activation of the primary loopback and test transmission modes. table 45. summary of the deactivation of sstsslb and sstsllb modes as a function of activating the primary loopback modes primary loopback mode deactivation of s-stsslb deactivation of s-stsllb stsslb if primary time slot = secondary if primary time slot = secondary stsllb if primary time slot = secondary if primary time slot = secondary blb always always cnubt if the secondary time slot is ts0 or if the primary time slot = secondary if primary time slot = secondary llb always always nuclb if the secondary time slot is ts0 or if the primary time slot = secondary if primary time slot = secondary pllb always always loopback mode will control that time slot. once selected, the desired time-slot position has the pro- grammable line idle code in register frm_pr22 transmitted to the line interface one frame before implementing the loopback and for the duration of the loopback. n the secondary-stsllb mode loops one and only one line time slot back to the line. the selected time slot data is looped to the line after being processed by the receive framer and it passes through the receive elastic store. the selected time slot has the programmable idle code in register frm_pr22 transmitted to the system interface one frame before implementing the loopback and for the duration of the loopback. in cept, selecting time slot 0 has the effect of deactivating the current loopback mode while no other action will be taken (time slot 0 will not be looped back to the line and should not be chosen in this mode). table 45 defines the deactivation of the two secondary loopback modes as a function of the activation of the primary loopback and test transmission modes. preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 90 lucent technologies inc. lucent technologies inc. alarms and performance monitoring (continued) figure 41 illustrates the various loopback modes implemented by each framer unit. 5-3914(f).cr.3 figure 41. loopback and test transmission modes framer framer line es system (3) single time-slot system loopback framer line es system (2) board loopback ais receive system data line system (1) line loopback is ignored insert only time slot x line es system (4) single time-slot line loopback transmit programmable idle code in register frm_pr22 line es system (5) cept nailed-up broadcast transmission transmit line ts-x in system ts-x and system ts-0 framer line es system (7) cept nailed-up connect loopback loopback ts-x in ts-0 transmit framer line system (6) payload line loopback transmit programmable line idle code in register frm_pr22 loopback ts-x in outgoing system ts-x in outgoing line ts-x lucent technologies inc. 91 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. alarms and performance monitoring (continued) line test patterns test patterns may be transmitted to the line through either register frm_pr20 or register frm_pr69. only one of these sources may be active at the same time. signaling must be inhibited while sending these test patterns. transmit line test patternsusing register frm_pr20 the transmit framer can be programmed through register frm_pr20 to transmit various test patterns. these test patterns, when enabled, overwrite the received chi data. the test patterns available using register frm_pr20 are: n the unframed-ais pattern which consists of a continuous bit stream of ones (. . . 111111 . . .) enabled by setting register frm_pr20 bit 0 to 1. n the unframed-auxiliary pattern which consists of a continuous bit stream of alternating ones and zeros (. . . 10101010 . . .) enabled by setting register frm_pr20 bit 1 to 1. n the quasi-random test signal, enabled by setting register frm_pr20 bit 3 to 1, which consists of: a pattern produced by means of a twenty-stage shift register with feedback taken from the 17th and 20th stages via an exclusive-or gate to the first stage. the output is taken from the 20th stage and is forced to a 1 state whenever the next 14 stages (19 through 6) are all 0. the pattern length is 1,048,575 or 2 20 C 1 bits. this pattern is described in detail in at&t technical reference 62411 [5] appendix and illustrated in figure 42. valid framing bits. valid transmit facility data link (tfdl) bit information. valid crc bits. 5-3915(f).dr.1 figure 42. 20-stage shift register used to generate the quasi-random signal n the pseudorandom test pattern, enabled by setting register frm_pr20 bit 2 to 1, which consists of: a 2 15 C 1 pattern inserted in the entire payload (time slots 124 in ds1 and time slots 132 in cept), as described by itu rec. 0.151 and illustrated in figure 43. valid framing pattern. valid transmit facility data link (tfdl) bit data. valid crc bits. d d-type flip-flops #1 dd #2 #17 d #18 dd #19 #20 a b c xor #6 #19 nor #20 quasi-random test output or preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 92 lucent technologies inc. lucent technologies inc. alarms and performance monitoring (continued) 5-3915(f).er.1 figure 43. 15-stage shift register used to generate the pseudorandom signal n the idle code test pattern, enabled by setting register frm_pr20 bit 6 to 1, which consists of: the programmable idle code, programmed through register frm_pr22, in time slots 124 in ds1 and 031 in cept. valid framing pattern. valid transmit facility data link (tfdl) bit data. valid crc bits. transmit line test patternsusing register frm_pr69 framed or unframed patterns indicated in table 46 may be generated and sent to the line by register frm_pr69 and by setting register frm_pr20 to 00 (hex). selection of transmission of either a framed or unframed test pat- tern is made through frm_pr69 bit 3. if one of the test patterns of register frm_pr69 is enabled, a single bit error can be inserted into the transmitted test pattern by toggling register frm_pr69 bit 1 from 0 to 1. table 46. register frm_pr69 test patterns pattern register frm_pr69 bit 7 bit 6 bit 5 bit 4 mark (all ones ais) 0 0 0 0 qrss (2 20 C 1 with zero suppression) 00 0 1 2 5 C 1 00 1 0 63 (2 6 C 1) 00 1 1 511 (2 9 C 1) 01 0 0 511 (2 9 C 1) reversed 01 0 1 2047 (2 11 C 1) 01 1 0 2047 (2 11 C 1) reversed 01 1 1 2 15 C 1 10 0 0 2 20 C 1 10 0 1 2 20 C 1 10 1 0 2 23 C 1 10 1 1 1:1 (alternating) 1 1 0 0 d xor d-type flip-flops #1 dd #2 #3 d #13 dd #14 #15 a b c pseudorandom test output lucent technologies inc. 93 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. alarms and performance monitoring (continued) receive line pattern monitorusing register frm_sr7 the receive framer pattern monitor continuously moni- tors the received line, detects the following fixed framed patterns, and indicates detection in register frm_sr7 bit 6 and bit 7. n the pseudorandom test pattern as described by itu rec. o.151 and illustrated in figure 43. detection of the pattern is indicated by register frm_sr7 bit 6 = 1. n the quasi-random test pattern described in at&t technical reference 62411[5] appendix and illus- trated in figure 42. detection of the pattern is indi- cated by register frm_sr7 bit 7 = 1. in ds1 mode, the received 193 bit frame must consist of 192 bits of pattern plus 1 bit of framing information. in cept mode, the received 256 bit frame must consist of 248 bits of pattern plus 8 bits (ts0) of framing infor- mation. no signaling, robbed bit in the case of t1 and ts16 signaling in the case of cept, may be present for successful detection of these two test patterns. to establish lock to the pattern, 256 sequential bits must be received without error. when lock to the pat- tern is achieved, the appropriate bit of register frm_sr7 is set to a 1. once pattern lock is estab- lished, the monitor can withstand up to 32 single bit errors per frame without a loss of lock. lock will be lost if more than 32 errors occur within a single frame. when such a condition occurs, the appropriate bit of register frm_sr7 is deasserted. the monitor then resumes scanning for pattern candidates. receive line pattern detectorusing register frm_pr70 framed or unframed patterns indicated in table 47 may be detected using register frm_pr70. detection of the selected test pattern is indicated when register frm_sr7 bit 4 is set to 1. selection of a framed or unframed test pattern is made through frm_pr70 bit 3. bit errors in the received test pattern are indicated when register frm_sr7 bit 5 = 1. the bit errors are counted and reported in registers frm_sr8 and frm_sr9, which are normally the bpv counter regis- ters. (in this test mode, the bpv counter registers do not count bpvs but count only bit errors in the received test pattern.) table 47. register frm_pr70 test patterns pattern register frm_pr70 bit 7 bit 6 bit 5 bit 4 mark (all ones ais) 0000 qrss (2 20 C 1 with zero suppression)0001 2 5 C 1 0010 63 (2 6 C 1) 0011 511 (2 9 C 1) 0100 511 (2 9 C 1) reversed 0101 2047 (2 11 C 1) 0110 2047 (2 11 C 1) reversed 0111 2 15 C 1 1000 2 20 C 1 1001 2 20 C 1 1010 2 23 C 1 1011 1:1 (alternating) 1100 preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 94 lucent technologies inc. lucent technologies inc. alarms and performance monitoring (continued) the pattern detector continuously monitors the received line for the particular pattern selected in register frm_pr70 bit 7bit 4 (dptrn). to establish detector lock to the pattern, 256 sequential bits must be detected. once the detector has locked onto the selected pattern, it will remain locked to the established alignment and count all unexpected bits as single bit errors until register frm_pr70 bit 2 (dblksel) is set to 0. to select a pattern or change the pattern to be detected, the following programming sequence must be followed. n dblksel (register frm_pr70 bit 2) is set to 0. n the new pattern to be detected is selected by setting register frm_pr70 bit 7bit 4 to the desired value. n dblksel (register frm_pr70 bit 2) is set to 1. lucent technologies inc. 95 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. alarms and performance monitoring (continued) automatic and on-demand commands various alarms can be transmitted either automatically as a result of various alarm conditions or on demand. after reset, all automatic transmissions are disabled. the user can enable the automatic or on-demand actions by set- ting the proper bits in the automatic and on-demand action registers as identified below in table 48. table 48 shows the programmable automatically transmitted signals and the triggering mechanisms for each. table 49 shows the on-demand commands. table 48. automatic enable commands action trigger enabling register bit transmit remote frame alarm (rfa) loss of frame alignment (rlfa). frm_pr27 bit 0 = 1 loss of cept time slot 16 multiframe alignment (rts16lmfa). frm_pr27 bit 1 = 1 loss of cept time slot 0 multiframe alignment (rts0lmfa). frm_pr27 bit 2 = 1 detection of the timer (100 ms or 400 ms) expiration due to loss of cept multiframe alignment. frm_pr27 bit 3 = 1 frm_pr9 bit 7bit 0 = 0xxxx1x1 or 0xxx1xx1 detection of the cept rsa6 = 8 (hex) code. frm_pr27 bit 4 = 1 detection of the cept rsa6 = c (hex) code. frm_pr27 bit 5 = 1 transmit cept e bit = 0 detection of cept crc-4 error. frm_pr28 bit 3 = 1 rts0lmfa. frm_pr28 bit 4 = 1 detection of the timer (100 ms or 400 ms) expiration due to loss of cept multiframe alignment. frm_pr28 bit 5 = 1 frm_pr9 bit 7bit 0 = 0xxxx1x1 or 0xxx1xx1 transmit ais to system rlfa. frm_pr19 bit 0 = 1 detection of the timer (100 ms or 400 ms) expiration due to loss of cept multiframe alignment. frm_pr19 bit 1 = 1 frm_pr9 bit 7bit 0 = 0xxxx1x1 or 0xxx1xx1 transmit cept time slot 16 remote multiframe alarm to line rts16lmfa. frm_pr41 bit 4 = 1 transmit cept ais in time slot 16 to system rts16lmfa. frm_pr44 bit 6 = 1 automatic enabling of ds1 line loopback on/off line loopback on/off code. frm_pr19 bit 4 =1 automatic enabling of esf fdl line loopback on/off esf line loopback on/off code. frm_pr19 bit 6 =1 automatic enabling of esf fdl payload loopback on/off esf payload loopback on/off code. frm_pr19 bit 7 =1 preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 96 lucent technologies inc. lucent technologies inc. alarms and performance monitoring (continued) table 49. on-demand commands type frame format action enabling register bit transmit remote frame alarm d4 (japanese) f s bit in frame 12 = 1. frm_pr27 bit 6 = 1 d4 (us) bit 2 of all time slots = 0. frm_pr27 bit 7 = 1 dds bit 6 in time slot 24 = 0. esf pattern of 1111111100000000 in the fdl f-bit position. cept a bit = 1. transmit time slot 16 remote multiframe alarm to the line cept time slot 16 remote alarm bit = 1. frm_pr41 bit 5 = 1 transmit data link ais (squelch) slc -96, esf transmit data link bit = 1. frm_pr21 bit 4 = 1 transmit line test patterns all transmit test patterns to the line interface. see line test patterns section on page 91 and transmit line test pat- ternsusing register frm_pr69 section on page 92. transmit system ais all transmits ais to the system. frm_pr19 bit 3 = 1 transmit system signaling ais (squelch) t1 transmit abcd = 1111 to the sys- tem. frm_pr44 bit 1 = 1 cept transmit ais in system time slot 16. frm_pr44 bit 7 = 1 receive signaling inhibit all suspend the updating of the receive signaling registers. frm_pr44 bit 3 = 1 receive framer reframe all force the receive framer to reframe. frm_pr26 bit 2 = 1 transmit line time slot 16 cept transmit ais in time slot 16 to the line. frm_pr41 bit 6 = 1 enable loopback all enables system and line loop- backs. see loopback and trans- mission modes section on page 88. framer software reset all the framer and fdl are placed in the reset state for four rclk clock cycles. the framer parameter reg- isters are forced to the default value. frm_pr26 bit 0 = 1 framer software restart all the framer and fdl are placed in the reset state as long as this bit is set to 1. the framer parameter reg- isters are not changed from their programmed values. frm_pr26 bit 1 = 1 lucent technologies inc. 97 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. facility data link (fdl) data may be extracted from and inserted into the facility data link in slc -96, dds, esf, and cept framing for- mats. in cept, any one of the sa bits can be declared as the facility data link by programming register frm_pr43 bit 0bit 2. access to the fdl is made through: n the fdl pins (rfdl, rfdlck, tfdl, and tfdlck). figure 28 shows the timing of these signals. n the 64-byte fifo of the fdl hdlc block. fdl information passing through the fdl hdlc section may beframed in hdlc format or passed through transparently . 5-3910(f).cr.1 figure 44. T7630 facility data link access timing of the transmit and receive framer sections in the esf frame format, automatic assembly and transmission of the performance report message (prm) as defined in both ansi t1.403-1995 and bellcores tr-tsy-000194 issue 1, 1287 is managed by the receive framer and transmit fdl sections. the ansi t1.403-1995 bit-oriented data link messages (bom) can be transmit- ted by the transmit fdl section and recognized and stored by the receive fdl section. receive facility data link interface summary a brief summary of the receive facility data link functions is given below: n bit-oriented message (bom) operation. the ansi t1.403-1995 bit-oriented data link messages are recog- nized and stored in register fdl_sr3. the number of times that an ansi code must be received for detection can be programmed from 1 to 10 by writing to register fdl_pr0 bit 4 bit 7. when a valid ansi code is detected, register fdl_sr0 bit 7 (fransi) is set. n hdlc operation. this is the default mode of operation when the fdl receiver is enabled (register fdl_pr1 bit 2 = 1). the hdlc framer detects the hdlc flags, checks the crc bytes, and stores the data in the fdl receiver fifo (register fdl_sr4) along with a status of frame (sf) byte. n hdlc operation with performance report messages (prm). this mode is enabled by setting register fdl_pr1 bit 2 and bit 6 to 1. in this case, the receive fdl will store the 13 bytes of the prm report field in the fdl receive fifo (register fdl_sr4) along with a status of frame (sf) byte. t8 t9 t9 t10 t11 t8: tfdlck cycle = t9: tfdl to tfdlck setup/hold = 40 ns t10: rfdlck cycle = t11: rfdlck to rfdl delay = 40 ns tfdlck tfdl rfdlck rfdl 250 m s (all other modes) 125 m s (dds) 250 m s (all other modes) 125 m s (dds) preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 98 lucent technologies inc. lucent technologies inc. facility data link (fdl) (continued) n transparent operation. enabling the fdl and setting register fdl_pr9 bit 6 (ftm) to 1 disables the hdlc processing. incoming data link bits are stored in the fdl receive fifo (register fdl_sr4). n transparent operation with pattern match. enabling the fdl and setting registers fdl_pr9 bit 5 (fmatch) and fdl_pr9 bit 6 (ftm) to 1 forces the fdl to start storing data in the fdl receive fifo (register fdl_sr4) only after the programmable match character defined in register fdl_pr8 bit 0bit 7 has been detected. the match character and all subsequent bytes are placed into the fdl receive fifo. the fdl interface to the receive framer is illustrated in figure 45. 5-4560(f).a figure 45. block diagram for the receive facility data link interface receive ansi t1.403 bit-oriented messages (bom) n the receive fdl monitor will detect any of the ansi t1.403 esf bit-oriented messages (boms) and generate an interrupt, enabled by register fdl_pr6 bit 7, upon detection. register fdl_sr0 bit 7 (fransi) is set to 1 upon detection of a valid bom and then cleared when read. n the received esf fdl bit-oriented messages are received in the form 111111110x 0 x 1 x 2 x 3 x 4 x 5 0 (the left-most bit is received first). the bits designated as x are the defined ansi esf fdl code bits. these code bits are writ- ten into the received ansi fdl status register fdl_sr3 when the entire code is received. n the minimum number of times a valid code must be received before it is reported can be programmed from 1 to 10 using register fdl_pr0 bit 4bit 7. receive line data receive framer loss of frame alignment receive fdl data extracter rfdl rfdlck receive facili ty data ansi t1.403-1995 bit-oriented data link messages monitor one 8-bit register identifying the esf bit-oriented code transparent microprocessor interface receive facility data link fifo receive facility data link hdlc rfdl rfdlck 64 8-bit locations lucent technologies inc. 99 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. facility data link (fdl) (continued) the received ansi fdl status byte, register fdl_sr3, has the following format. table 50. receive ansi code receive ansi performance report messages (prm) as defined in ansi t1.403, the performance report messages consist of 15 bytes, starting and ending with an hdlc flag. the receive framer status information consists of four pairs of octets, as shown in table 51. upon detection of the prm message, the receive fdl extracts the 13 bytes of the prm report field and stores it in the receive fdl fifo along with the status of frame byte. table 51. performance report message structure* * the rightmost bit (bit 1) is transmitted first for all fields except for the 2 bytes of the fcs that are transmitted leftmost bit (bit 8) first. the definition of each prm field is shown in table 52, and octet content is shown in table 53. b7 b6 b5 b4 b3 b2 b1 b0 00x 5 x 4 x 3 x 2 x 1 x 0 octet number prm b7 prm b6 prm b5 prm b4 prm b3 prm b2 prm b1 prm b0 1flag 2 sapi c/r ea 3 tei ea 4 control 5 g3lvg4u1u2g5slg6 6 feselbg1 r g2nmnl 7 g3lvg4u1u2g5slg6 8 feselbg1 r g2nmnl 9 g3lvg4u1u2g5slg6 10 fe se lb g1 r g2 nm nl 11 g3 lv g4 u1 u2 g5 sl g6 12 fe se lb g1 r g2 nm nl 1314 fcs 15 flag preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 100 lucent technologies inc. lucent technologies inc. facility data link (fdl) (continued) table 52. fdl performance report message field definition table 53. octet contents and definition prm field definition g1 = 1 crc error event = 1 g2 = 1 1 < crc error event 5 g3 = 1 5 < crc error event 10 g4 = 1 10 < crc error event 100 g5 = 1 100 < crc error event 319 g6 = 1 crc error event 3 320 se = 1 severely errored framing event 3 1 (fe will = 0) fe =1 frame synchronization bit error event 3 1 (se will = 0) lv = 1 line code violation event 3 1 sl = 1 slip event 3 1 lb = 1 payload loopback activated u1, u2 = 0 reserved r = 0 reserved (default value = 0) nm, nl = 00, 01, 10, 11 one-second report modulo 4 counter octet number octet contents definition 1 01111110 opening lapd flag 2 00111000 00111010 from ci: sapi = 14, c/r = 0, ea = 0 from carrier: sapi = 14, c/r = 1, ea = 0 3 00000001 tei = 0, ea = 1 4 00000011 unacknowledged frame 5, 6 variable data for latest second (t) 7, 8 variable data for previous second (t C 1) 9, 10 variable data for earlier second (t C 2) 11, 12 variable data for earlier second (t C 3) 13, 14 variable crc-16 frame check sequence 15 01111110 closing lapd flag lucent technologies inc. 101 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) lucent technologies inc. facility data link (fdl) (continued) receive hdlc mode this is the default mode of the fdl. the receive fdl receives serial data from the receive framer, identifies hdlc frames, reconstructs data bytes, provides bit destuffing as necessary, and loads parallel data in the receive fifo. the receive queue manager forms a status of frame (sf) byte for each hdlc frame and stores the sf byte in the receive fdl fifo (register fdl_sr4) after the last data byte of the associated frame. hdlc frames consisting of n bytes will have n + 1 bytes stored in the receive fifo. the frame check sequence bytes (crc) of the received hdlc frame are not stored in the receive fifo. when receiving ansi prm frames, the frame check sequence bytes are stored in the receive fifo. the sf byte has the following format. table 54. receive status of frame byte rsf b7 rsf b6 rsf b5 rsf b4 rsf b3 rsf b2 rsf b1 rsf b0 bad crc abort rfifo overrun bad byte count 0000 bit 7 of the sf status byte is the crc status bit. a 1 indicates that an incorrect crc was detected. a 0 indi- cates the crc is correct. bit 6 of the sf status byte is the abort status. a 1 indicates the frame associated with this status byte was aborted (i.e., the abort sequence was detected after an opening flag and before a subsequent closing flag). an abort can also cause bits 7 and/or 4 to be set to 1. an abort is not reported when a flag is followed by seven ones. bit 5 is the fifo overrun bit. a 1 indicates that a receive fifo overrun occurred (the 64-byte fifo size was exceeded). bit 4 is the fifo bad byte count that indi- cates whether or not the bit count received was a multi- ple of eight (i.e., an integer number of bytes). a 1 indicates that the bit count received after 0-bit deletion was not a multiple of eight, and a 0 indicates that the bit count was a multiple of eight. when a nonbyte-aligned frame is received, all bits received are present in the receive fifo. the byte before the sf status byte con- tains less than eight valid data bits. the hdlc block provides no indication of how many of the bits in the byte are valid. user application programming controls processing of nonbyte-aligned frames. bit 3bit 0 of the sf status byte are not used and are set to 0. a good frame is implied when the sf status byte is 00 (hex). receive fdl fifo whenever an sf byte is present in the receive fifo, the end of frame registers fdl_sr0 bit 4 (freof) and fdl_sr2 bit 7 (feof) bits are set. the receiver queue status (register fdl_sr2 bit 0bit 6) bits report the number of bytes up to and including the first sf byte. if no sf byte is present in the receive fifo, the count directly reflects the number of data bytes available to be read. depending on the fdl frame size, it is possi- ble for multiple frames to be present in the receive fifo. the receive fill level indicator register fdl_pr6 bit 0bit 5 (fril) can be programmed to tailor the ser- vice time interval to the system. the receive fifo full register fdl_sr0 bit 3 (frf) interrupt is set in the interrupt status register when the receive fifo reaches the preprogrammed full position. an freof interrupt is also issued when the receiver has identified the end of frame and has written the sf byte for that frame. an fdl overrun interrupt register fdl_sr0 bit 5 (froverun) is generated when the receiver needs to write either status or data to the receive fifo while the receive fifo is full. an overrun condition will cause the last byte of the receive fifo to be overwritten with an sf byte indicating the overrun status. a receive idle register fdl_sr0 bit 6 (fridl) interrupt is issued whenever 15 or more continuous ones have been detected. preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 102 lucent technologies inc. lucent technologies inc. facility data link (fdl) (continued) the receive queue status bits, register fdl_sr2 bit 0bit 6 (frqs), are updated as bytes are loaded into the receive fifo. the sf status byte is included in the byte count. when the first sf status byte is placed in the fifo, register fdl_sr0 bit 4 (freof) is set to 1, and the status freezes until the fifo is read. as bytes are read from the fifo, the queue status decrements until it reads 1. the byte read when register fdl_sr2 bit 0bit 6 = 0000001 and the freof bit is 1 is the sf status byte describing the error status of the frame just read. once the first sf status byte is read from the fifo, the fifo status is updated to report the number of bytes to the next sf status byte, if any, or the number of additional bytes present. when freof is 0, no sf status byte is currently present in the fifo, and the frqs bits report the number of bytes present. as bytes are read from the fifo, the queue status decrements with each read until it reads 0 when the fifo is totally empty. the freof bit is also 0 when the fifo is completely empty. thus, the frqs and freof bits provide a mechanism to recognize the end of 1 frame and the beginning of another. reading the fdl receiver status register does not affect the fifo buffers. in the event of a receiver overrun, an sf status byte is written to the receive fifo. multiple sf status bytes can be present in the fifo. the frqs reports only the number of bytes to the first sf status byte. if frqs is 0, do not read the receive fifo. a read will result in corruption of receive fifo. to allow users to tailor receiver fifo service intervals to their systems, the receiver interrupt level bits in register fdl_pr6 bit 0bit 5 (fril) are provided. these bits are coded in binary and determine when the receiver full interrupt, register fdl_sr0 bit 3 (frf), is asserted. the interrupt pin transition can be masked by setting register fdl_pr2 bit 3 (frfie) to 0. the value programmed in the fril bits equals the total number of bytes necessary to be present in the fifo to trigger an frf interrupt. the frf interrupt alone is not sufficient to determine the number of bytes to read, since some of the bytes may be sf status bytes. the frqs bits and freof bit allow the user to determine the number of bytes to read. the freof interrupt can be the only interrupt for the final frame of a group of frames, since the number of bytes received to the end of the frame cannot be sufficient to trigger an frf interrupt. programming note: since the receiver writing to the receive fifo and the host reading from the receive fifo are asynchronous events, it is possible for a host read to put the number of bytes in the receive fifo just below the programmed fril level and a receiver write to put it back above the fril level. this causes a new frf interrupt and has the potential to cause software problems. it is recommended that during service of the frf interrupt, the frf interrupt be masked frfie = 0 and the interrupt register be read at the end of the service routine, discarding any frf interrupt seen before unmasking the frf interrupt. receiver overrun a receiver overrun occurs if the 64-byte limit of the receiver fifo is exceeded, i.e., data has been received faster than it has been read out of the receive fifo. upon overrun, an sf status byte with the overrun bit (bit 5) set to 1 replaces the last byte in the fifo. the sf status byte can have other error conditions present. for example, it is unlikely the crc is correct. thus, care should be taken to prioritize the possible frame errors in the software service routine. the last byte in the fifo is overwritten with the sf status byte regardless of the type of byte (data or sf status) being overwritten. the overrun condition is reported in register fdl_sr0 bit 5 and causes the interrupt pin to be asserted if it is not masked (register fdl_pr2 bit 5 (frovie)). data is ignored until the condition is cleared and a new frame begins. the overrun condition is cleared by reading register fdl_sr0 bit 5 and reading at least 1 byte from the receive fifo. because multiple frames can be present in the fifo, good frames as well as the overrun frame can be present. the host can determine the overrun frame by looking at the sf status byte. lucent technologies inc. 103 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. facility data link (fdl) (continued) transmit facility data link interface the fdl interface of the transmit framer is shown in figure 46, indicating the priority of the fdl sources. the remote frame alarm, enabled using register frm_pr27, is given the highest transmission priority by the trans- mit framer. the ansi t1.403-1995 bit-oriented data link message transmission is given priority over performance report mes- sages, and the automatic transmission of the performance report messages is given priority over fdl hdlc trans- mission. idle code is generated by the fdl unit when no other transmission is enabled. the fdl transmitter is enabled by setting register fdl_pr1 bit 3 to 1. 5-4561(f).a figure 46. block diagram for the transmit facility data link interface tra nsmit ansi t1.403 bit-oriented messages (bom) when the ansi bom mode is enabled by setting register fdl_pr10 bit 7 to 1, the transmit fdl can send any of the ansi t1.403 esf bit-oriented messages automatically through the fdl bit in the frame. the transmit esf fdl bit-oriented messages of the form 111111110x 0 x 1 x 2 x 3 x 4 x 5 0 are taken from the transmit ansi fdl parameter register fdl_pr10 bit 0bit 5. the esf fdl bit-oriented messages will be repeated while register fdl_pr10 bit 7 (ftansi) is set to 1. microprocessor interface transmit fdl fifo receive framer transmit fdl hdlc framer transmit fdl clock generator transparent tfdl tfdlck tfdlck transmit performance report message assembler transmit ansi t1.403 fdl bit code generator fdl idle code generator fdl yellow alarm transmit frame assembler preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 104 lucent technologies inc. lucent technologies inc. facility data link (fdl) (continued) trans mit ansi performance report messages (prm) when the ansi prm mode is enabled by setting register fdl_pr1 bit 7 to 1, the transmit fdl assembles and transmits the ansi performance report message once every second. after assembling the ansi prm message, the receive framer stores the current second of the message in regis- ters frm_sr62 and frm_sr63 and transfers the data to the fdl transmit fifo. after accumulating three sec- onds (8 bytes) of the message, the fdl transmit block appends the header and the trailer (including the opening and closing flags) to the prm messages and transmits it to the framer for transmission to the line. tables 5153 show the complete format of the prm hdlc packet. hdlc operation hdlc operation is the default mode of operation. the transmitter accepts parallel data from the transmit fifo, con- verts it to a serial bit stream, provides bit stuffing as necessary, adds the crc-16 and the opening and closing flags, and sends the framed serial bit stream to the transmit framer. hdlc frames on the serial link have the follow- ing format. table 55. hdlc frame format all bits between the opening flag and the crc are considered user data bits. user data bits such as the address, control, and information fields for lapb or lapd frames are fetched from the transmit fifo for transmission. the 16 bits preceding the closing flag are the frame check sequence, cyclic redundancy check (crc), bits. zero-bit insertion/deletion (bit stuffing/destuffing) the hdlc protocol recognizes three special bit patterns: flags, aborts, and idles. these patterns have the common characteristic of containing at least six consecutive ones. a user data byte can contain one of these special pat- terns. transmitter zero-bit stuffing is done on user data and crc fields of the frame to avoid transmitting one of these special patterns. whenever five ones occur between flags, a 0 bit is automatically inserted after the fifth 1, prior to transmission of the next bit. on the receive side, if five successive ones are detected followed by a 0, the 0 is assumed to have been inserted and is deleted (bit destuffing). opening flag user data field frame check sequence (crc) closing flag 01111110 3 8 bits 16 bits 01111110 lucent technologies inc. 105 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. facility data link (fdl) (continued) flags * all flags have the bit pattern 01111110 and are used for frame synchronization. the fdl hdlc block automati- cally sends two flags between frames. if the chip-con- figuration register fdl_pr0 bit 1 (flags) is cleared to 0, the ones idle byte (11111111) is sent between frames if no data is present in the fifo. if flags is set to 1, the fdl hdlc block sends continuous flags when the transmit fifo is empty. the fdl hdlc does not transmit consecutive frames with a shared flag; there- fore, two successive flags will not share the intermedi- ate 0. an opening flag is generated at the beginning of a frame (indicated by the presence of data in the transmit fifo and the transmitter enable register fdl_pr1 bit 3 = 1). data is transmitted per the hdlc protocol until a byte is read from the fifo while register fdl_pr3 bit 7 (ftfc) set to 1. the fdl hdlc block follows this last user data byte with the crc sequence and a clos- ing flag. the receiver recognizes the 01111110 pattern as a flag. two successive flags may or may not share the intermediate 0 bit and are identified as two flags (i.e., both 011111101111110 and 0111111001111110 are recognized as flags by the fdl hdlc block). when the second flag is identified, it is treated as the closing flag. as mentioned above, a flag sequence in the user data or crc bits is prevented by zero-bit insertion and dele- tion. the hdlc receiver recognizes a single flag between frames as both a closing and opening flag. aborts an abort is indicated by the bit pattern of the sequence 01111111. a frame can be aborted by writing a 1 to register fdl_pr3 bit 6 (ftabt). this causes the last byte written to the transmit fifo to be replaced with the abort sequence upon transmission. once a byte is tagged by a write to ftabt, it cannot be cleared by subsequent writes to register fdl_pr3. ftabt has higher priority than fdl transmit frame complete (ftfc), but ftabt and ftfc should never be set to 1 simultaneously since this causes the transmitter to enter an invalid state requiring a transmitter reset to clear. a frame should not be aborted in the very first byte following the opening flag. an easy way to avoid this situation is to first write a dummy byte into the queue and then write the abort command to the queue. when receiving a frame, the receiver recognizes the abort sequence whenever it receives a 0 followed by seven consecutive ones. the receive fdl unit will abort a frame whenever the receive framer detects a loss of frame alignment. this results in the abort bit, and possibly the bad byte count bit and/or bad crc bits, being set in the status of frame status byte (see table 54) which is appended to the receive data queue. all subsequent bytes are ignored until a valid opening flag is received. idles in accordance with the hdlc protocol, the hdlc block recognizes 15 or more contiguous received ones as idle. when the hdlc block receives 15 contiguous ones, the receiver idle bit register fdl_sr0 bit 6 (ridl) is set. for transmission, the ones idle byte is defined as the binary pattern 11111111 (ff (hex)). if the flags con- trol bit in register fdl_pr0 bit 1 is 0, the ones idle byte is sent as the time-fill byte between frames. a time-fill byte is sent when the transmit fifo is empty and the transmitter has completed transmission of all previous frames. frames are sent back-to-back otherwise. crc-16 for given user data bits, 16 additional bits that consti- tute an error-detecting code (crc-16) are added by the transmitter. as called for in the hdlc protocol, the frame check sequence bits are transmitted most signifi- cant bit first and are bit stuffed. the cyclic redundancy check (or frame check sequence) is calculated as a function of the transmitted bits by using the itu-t stan- dard polynomial: x 16 + x 12 + x 5 + 1 the transmitter can be instructed to transmit a cor- rupted crc by setting register fdl_pr2 bit 7 (ftb- crc) to 1. as long as the ftbcrc bit is set, the crc is corrupted for each frame transmitted by logically flip- ping the least significant bit of the transmitted crc. the receiver performs the same calculation on the received bits after destuffing and compares the results to the received crc-16 bits. an error indication occurs if, and only if, there is a mismatch. * regardless of the time-fill byte used, there always is an opening and closing flag with each frame. back-to-back frames are sepa- rated by two flags. preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 106 lucent technologies inc. lucent technologies inc. facility data link (fdl) (continued) transmit fdl fifo transmit fdl data is loaded into the 64-byte transmit fifo via the transmit fdl data register, fdl_pr4. the transmit fdl status register indicates how many addi- tional bytes can be added to the transmit fifo. the transmit fdl interrupt trigger level register fdl_pr3 bit 0bit 5 (ftil) can be programmed to tailor service time intervals to the system environment. the transmit- ter empty interrupt bit is set in the fdl interrupt status register fdl_sr0 bit 1 (ftem) when the transmit fifo has sufficient empty space to add the number of bytes specified in register fdl_pr3 bit 0bit 5. there is no interrupt indicated for a transmitter overrun that is writing more data than empty spaces exist. overrun- ning the transmitter causes the last valid data byte writ- ten to be repeatedly overwritten, resulting in missing data in the frame. data associated with multiple frames can be written to the transmit fifo by the controlling microprocessor. however, all frames must be explicitly tagged with a transmit frame complete, register fdl_pr3 bit 7 (ftfc), or a transmit abort, register fdl_pr3 bit 6 (ftabt). the ftfc is tagged onto the last byte of a frame written into the transmitter fifo and instructs the transmitter to end the frame and attach the crc and closing flag following the tagged byte. once written, the ftfc cannot be changed by another write to register fdl_pr3. if ftfc is not written before the last data byte is read out for transmission, an underrun occurs (fdl_sr0 bit 2). when the transmitter has completed a frame, with a closing flag or an abort sequence, reg- ister fdl_sr0 bit 0 (ftdone) is set to 1. an interrupt is generated if fdl_pr2 bit 0 (ftdie) is set to 1. sending 1-byte frames sending 1-byte frames with an empty transmit fifo is not recommended. if the fifo is empty, writing two data bytes to the fifo before setting ftfc provides a minimum of eight tfdlck periods to set ftfc. when 1 byte is written to the fifo, ftfc must be written within 1 tfdlck period to guarantee that it is effective. thus, 1-byte frames are subject to underrun aborts. one-byte frames cannot be aborted with ftabt. plac- ing the transmitter in ones-idle mode, register fdl_pr0 bit 1 (flags) = 0, lessens the frequency of underruns. if the transmit fifo is not empty, then 1-byte frames present no problems. transmitter underrun after writing a byte to the transmit queue, the user has eight tfdlck cycles in which to write the next byte before a transmitter underrun occurs. an underrun occurs when the transmitter has finished transmitting all the bytes in the queue, but the frame has not yet been closed by setting ftfc. when a transmitter underrun occurs, the abort sequence is sent at the end of the last valid byte transmitted. a ftdone interrupt is generated, and the transmitter reports an underrun abort until the interrupt status register is read. using the transmitter status and fill level the transmitter-interrupt level bits, register fdl_pr3 bit 0bit 5, allow the user to instruct the fdl hdlc block to interrupt the host processor whenever the transmitter has a predetermined number of empty loca- tions. the number of locations selected determines the time between transmitter empty, register frm_sr0 bit 1 (ftem), interrupts. the transmitter status bits, regis- ter fdl_sr1, report the number of empty locations in the fdl transmitter fifo. the transmitter empty dynamic bit, register fdl_sr1 bit 7 (fted), like the ftem interrupt bit, is set to 1 when the number of empty locations is less than or equal to the pro- grammed empty level. fted returns to 0 when the transmitter is filled to above the programmed empty level. polled interrupt systems can use fted to deter- mine when they can write to the fdl transmit fifo. lucent technologies inc. 107 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. facility data link (fdl) (continued) transparent mode the fdl hdlc block can be programmed to operate in the transparent mode by setting register fdl_pr9 bit 6 (ftrans) to 1. in the transparent mode of operation, no hdlc processing is performed on user data. the transparent mode can be exited at any time by setting fdl_pr9 bit 6 (ftrans) to 0. it is recommended that the transmitter be disabled when changing in and out of transparent mode. the transmitter should be reset by setting fdl_pr1 bit 5 (ftr) to 1 whenever the mode is changed. in the transmit direction, the fdl hdlc takes data from the transmit fifo and transmits that data exactly bit-for-bit on the tfdl interface. transmit data is octet- aligned to the first tfdlck after the transmitter has been enabled. the bits are transmitted least significant bit first. when there is no data in the transmit fifo, the fdl hdlc either transmits all ones, or transmits the programmed hdlc transmitter idle character (register fdl_pr5) if register fdl_pr9 bit 6 (fmatch) is set to 1. to cause the transmit idle character to be sent first, the character must be programmed before the transmitter is enabled. the transmitter empty interrupt, register fdl_sr0 bit 1 (ftem), acts as in the hdlc mode. the transmitter- done interrupt, register fdl_sr0 bit 0 (ftdone), is used to report an empty fdl transmit fifo. the ftdone interrupt thus provides a way to determine transmission end. register fdl_sr0 bit 2 (ftundabt) interrupt is not active in the transparent mode. in the receive direction, the fdl hdlc block loads received data from the rfdl interface directly into the receive fifo bit-for-bit. the data is assumed to be least significant bit first. if fmatch register fdl_pr9 bit 6 is 0, the receiver begins loading data into the receive fifo beginning with the first rfdlck detected after the receiver has been enabled. if the fmatch bit is set to 1, the receiver does not begin loading data into the fifo until the receiver match character has been detected. the search for the receiver match character is in a sliding window fashion if register fdl_pr9 bit 4 (faloct) bit is 0 (align to octet), or only on octet boundaries if faloct is set to 1. the octet boundary is aligned relative to the first rfdlck after the receiver has been enabled. the matched character and all sub- sequent bytes are placed in the receive fifo. an fdl receiver reset, register fdl_pr1 bit 4 (frr) = 1, causes the receiver to realign to the match character if fmatch is set to 1. the receiver full (frf) and receiver overrun (froverun) interrupts in register fdl_sr0 act as in the hdlc mode. the received end of frame (freof) and receiver idle (fridl) interrupts are not used in the transparent mode. the match status (fmstat) bit is set to 1 when the receiver match character is first rec- ognized. if the fmatch bit is 0, the fmstat (fdl_pr9 bit 3) bit is set to 1 automatically when the first bit is received, and the octet offset status bits (fdl_pr9 bit 0bit 2) read 000. if the fmatch bit is programmed to 1, the fmstat bit is set to 1 upon rec- ognition of the first receiver match character, and the octet offset status bits indicate the offset relative to the octet boundary at which the receiver match character was recognized. the octet offset status bits have no meaning until the fmstat bit is set to 1. an octet offset of 111 indicates byte alignment. an interrupt for recognition of the match character can be generated by setting the fril level to 1. since the matched character is the first byte written to the fifo, the frf interrupt occurs with the writing of the match character to the receive fifo. programming note: the match bit (fmatch) affects both the transmitter and the receiver. care should be taken to correctly program both the transmit idle char- acter and the receive match character before setting fmatch. if the transmit idle character is programmed to ff (hex), the fmatch bit appears to affect only the receiver. preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 108 lucent technologies inc. lucent technologies inc. facility data link (fdl) (continued) the operation of the receiver in transparent mode is summarized in table 56. table 56. receiver operation in transparent mode diagnostic modes loopbacks the serial link interface can operate in two diagnostic loopback modes: (1) local loopback and (2) remote loopback. the local loopback mode is selected when register fdl_pr1 bit 1 (fllb) is set to 1. the remote loopback is selected when register fdl_pr1 bit 0 (frlb) is set to 1. for normal traffic, i.e., to operate the transmitter and receiver independently, the fllp bit and the frlb bits should both be cleared to 0. local and remote loopbacks cannot be enabled simultaneously. in the local loopback mode: n tfdlck clocks both the transmitter and the receiver. n the transmitter and receiver must both be enabled. n the transmitter output is internally connected to the receiver input. n the tfdl is active. n the rfdl input is ignored. n the communication between the transmit and receive fifo buffers and the microprocessor continues normally. faloct fmatch receiver operation x 0 serial-to-parallel conversion begins with first rfdlck after fre, register fdl_pr1 bit 2, is set. data loaded to receive fifo immediately. 0 1 match user-defined character using sliding window. byte aligns once character is recognized. no data to receive fifo until match is detected. 1 1 match user-defined character, but only on octet boundary. boundary based on first rfdlck after fre, register fdl_pr1 bit 2, set. no data to receive fifo until match is detected. lucent technologies inc. 109 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. facility data link (fdl) (continued) 5-4562(f)r.2 figure 47. local loopback mode in the remote loopback mode: n transmitted data is retimed with a maximum delay of 2 bits. n received data is retransmitted on the tfdl. n the transmitter should be disabled. the receiver can be disabled or enabled. received data is sent as usual to the receive fifo if the receiver is denabled. 5-4563(f)r.1 figure 48. remote loopback mode xmit hdlc fdl block xmit hdlc fdl xmit interface xmit fifo rcvr fifo rcvr hdlc fdl rcvr interface tfdl tfdlck rfdlck rfdl rcvr hdlc fdl block xmit hdlc fdl block xmit hdlc fdl xmit interface xmit fifo rcvr fifo rcvr hdlc fdl rcvr interface tfdl tfdlck rfdlck rfdl rcvr hdlc fdl block preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 110 lucent technologies inc. lucent technologies inc. phase-lock loop circuit the T7630 allows for independent transmit path and receive path clocking. the device provides outputs to control variable clock oscillators on both the transmit and receive paths. as such, the system may have both the transmit and receive paths phase-locked to two autonomous clock sources. the block diagram of the T7630 phase detector cir- cuitry is shown in figure 49. the T7630 uses elastic store buffers (two frames) to accommodate the transfer of data from the system interface clock rate of 2.048 mbits/s to the line interface clock rate of either 1.544 mbits/s or 2.048 mbits/s. the transmit line side of the T7630 does not have any mechanism to monitor data overruns or underruns (slips) in its elastic store buffer. this interface relies on the requirement that the pllck clock signal (variable) is phase-locked to the rchick clock signal (reference). when this require- ment is not met, uncontrolled slips may occur in the transmit elastic store buffer that would result in corrupt- ing data and no indication will be given. typically, a variable clock oscillator (vcxo) is used to drive the pllck signal. the T7630 provides a phase error sig- nal (pllck-epll) that can be used to control the vcxo. the pllck-epll signal is generated by moni- toring the divided-down pllck (div-pllck) and rchick (div-rchick) signals. the div-rchick sig- nal is used as the reference to determine the phase dif- ference between div-rchick and div-pllck. while div-rchick and divpllck are phase-locked, the pllck-epll signal is in a high-impedance state. a phase difference between div-rchick and div- pllck drives pllck-epll to either 5 v or 0 v. an appropriate loop filter, for example, an rc circuit with r = 1 k w and c = 0.1 m f) is used to filter these pllck- epll pulses to control the vcxo. the system can force tchick to be phase-locked to rlck by using rlck as a reference signal to control a vcxo that is sourcing the tchick signal. the T7630 uses the receive line signal (rlck) as the reference and the tchick signal as the variable signal. the T7630 provides a phase error signal (tchick-epll) that can be used to control the vcxo generating tch- ick. the tchick-epll signal is generated by moni- toring the divided-down tchick signal (div-tchick) and rlck (div-rlck) signals. the div-rlck signal is used as the reference to determine the phase differ- ence between div-tchick and div-rlck. while div- rlck and div-tchick are phase-locked, the tch- ick-epll signal is in a high-impedance state. a phase difference between div-rlck and div-tchick drives tchick-epll to either 5 v or 0 v. an appropriate loop filter, for example, an rc circuit with r = 1 k w and c = 0.1 m f, is used to filter these tchick-epll pulses to control the vcxo. in this mode, the T7630 can be programmed to act as a master timing source and is capable of generating the system frame synchroniza- tion signal through the tchifs pin by setting frm_pr45 bit 4 to 1. lucent technologies inc. 111 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. phase-lock loop circuit (continued) 5-5268(f)r.2 figure 49. T7630 phase detector circuitry tpd, tnd tlck transmit framer receive concentration highway interface rchidata rchick rchifs transmit concentration highway interface receive 2-frame elastic store buffer receive framer rpd, rnd rlck read address transmit 2-frame elastic store buffer pllck divider circuit internal_xlck pllck div-pllck digital phase detector rchick divider circuit pllck-epll div-rchick voltage- controlled crystal oscillator (vcxo) tchick tchidata tchifs system data write address system data read address facility data write address facility data slip monitor buffer overrun buffer underrun rlck divider circuit digital phase detector tchick divider circuit div-rlck div-tchick tchick_epll voltage- controlled crystal oscillator (vcxo) internal_tchick internal_rlck internal_rchick external circuit external circuit preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 112 lucent technologies inc. lucent technologies inc. framer-system (chi) interface ds1 modes the ds1 framing formats require rate adaptation from the 1.544 mbits/s line interface bit stream to the system interface which functions at multiples of a 2.048 mbits/s bit stream. the rate adaptation results in the need for eight stuffed time slots on the system interface since there are only 24 ds1 (1.544 mbits/s) payload time slots while there are 32 system (2.048 mbits/s) time slots. placement of the stuffed time slots is defined by register frm_pr43 bit 0bit 2. cept modes the framer maps the line time slots into the corre- sponding system time slot one-to-one. framing time slot 0, the fas and nfas bytes, are placed in system time slot 0. receive elastic store the receive interface between the framer and the sys- tem (chi) includes a two-frame elastic store buffer to enable rate adaptation. the receive line elastic store buffer contains circuitry that monitors the read and write pointers for potential data overrun and underrun (slips) conditions. whenever this slip circuitry deter- mines that a slip may occur in the receive elastic store buffer, it will adjust the read pointer such that a con- trolled slip is performed. the controlled slip is imple- mented by dropping or repeating a complete frame at the frame boundaries. the occurrence of controlled slips in the receive elastic store are indicated in the sta- tus register frm_sr3 bit 6 and bit 7. transmit elastic store the transmit interface between the framer and the sys- tem (chi) includes a two-frame elastic store buffer to enable rate adaptation. the line transmit clock applied to pllck (pins 7/31) must be phase-locked to rchick. no indication of a slip in the transmit elastic store is given. concentration highway interface each framer has a dual, high-speed, serial interface to the system known as the chi. this flexible bus archi- tecture allows the user to directly interface to other lucent components which use this interface, as well as to mitel * and amd ? tdm highway interfaces, with no glue logic. configured via the highway control registers frm_pr45 through frm_pr66, this interface can be set up in a number of different configurations. the following is a list of the chi features: n lucent technologies standard interface for communi- cation devices. n two pairs of transmit and receive paths to carry data in 8-bit time slots. n programmable definition of highways through offset and clock-edge options which are independent for transmit and receive directions. n programmable idle code substitution of received time slots. n programmable 3-state control of each transmit time slot. n independent transmit and receive framing signals to synchronize each direction of data flow. n an 8 khz frame synchronization signal internally generated from the received line clock. n compatible with mitel and amd pcm highways. supported is the optional configuration of the chi which presents the signaling information along with the data in any framing modes when the device is pro- grammed for the associated signaling mode (asm). this mode is discussed in the signaling section. data can be transmitted or received on either one of two interface ports, called chidata and chidatab. the user-supplied clocks (rchiclk and tchiclk) control the timing on the transmit or receive paths. indi- vidual time slots are referenced to the frame synchroni- zation (rchifs and tchifs) pulses. each frame consists of 32 time slots at a programmable data rate of 2.048 mbits/s, 4.096 mbits/s, or 8.192 mbits/s requiring a clock (tchick and rchick) of the same rate. the clock and data rates of the transmit and receive high- ways are programmed independently. * mitel is a registered trademark of mitel corporation. ? amd is a registered trademark of advanced micro devices, inc. lucent technologies inc. 113 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. concentration highway interface (continued) rate adaptation is required for all ds1 formats between the 1.544 mbits/s line rate and 2.048 mbits/s, 4.966 mbits/s, or 8.182 mbits/s chi rate. this is achieved by means of stuffing eight idle time slots into the existing twenty-four time slots of the t1 frame. idle time slots can occur every fourth time slot (starting in the first, second, third, or fourth time slot) or be grouped together at the end of the chi frame as described in register frm_pr43 bit 0bit 2. the positioning of the idle time slots is the same for transmit and receive directions. idle time slots con- tain the programmable code of register frm_pr23. unused time slots can be disabled by forcing the tchidata interface to a high-impedance state for the interval of the disabled time slots. chi parameters the chi parameters that define the receive and transmit paths are given in table 57. table 57. summary of the T7630s concentration highway interface parameters name description hwyen highway enable (frm_pr45 bit 7). a 1 in this bit enables the transmit and receive concentration highway interfaces. this allows the framer to be fully configured before transmission to the highway. a 0 forces the idle code as defined in register frm_pr22, to be transmitted to the line in all payload time slots while tchidata is forced to a high-impedance state for all chi transmitted time slots. chimm concentration highway master mode (prm_pr45 bit 4). the default mode chimm = 0 enables an external system frame synchronization signal (tchifs) to drive the transmit chi. a 1 enables the transmit chi to generate a system frame syn- chronization signal from the receive line clock. the transmit chi system frame syn- chronization signal is generated on the tchifs output pin. applications using the receive line clock as the reference clock signal of the system are recommended to enable this mode and use the tchifs signal generated by the framer. the receive chi path is not affected by this mode. chidts chi double time-slot mode (frm_pr65 bit 1 and frm_pr66 bit 1). chidts defines the 4.096 mbits/s and 8.192 mbits/s chi modes. chidts = 0 enables the 32 contiguous time-slot mode. this is the default mode. chidts = 1 enables the double time-slot mode in which the transmit chi drives tchidata for one time slot and then 3-states for the subsequent time slot, and the receive chi latches data from rchi- data for one time slot and then ignores the following time slot and so on. chidts = 1 allows two chis to interleave frames on a common bus. tfe transmit frame edge (frm_pr46 bit 3). tfe = 0 (or 1), tchifs is sampled on the falling (or rising) edge of tchick. in chimm (chi master mode), the tchifs pin outputs a transmit frame strobe to provide synchronization for tchidata. when tfe = 1 (or 0), tchifs is centered around rising (or falling) edge of tchick. in this mode, tchifs can be used for receive data on rchidata. the timing for tchifs in chimm = 1 mode is identical to the timing for tchifs in chimm = 0 mode. rfe receive frame edge (frm_pr46 bit 7). rfe = 0 (or 1), rchifs is sampled on the falling (or rising) edge of rchick. cdrs0cdrs1 chi data rate (frm_pr45 bit 2 and bit 3). two-bit control for selecting the chi data rate. the default state (00) enables the 2.048 mbits/s. cdrs bit:2 3chi data rate 0 0 2.048 mbits/s 0 1 4.096 mbits/s 1 0 8.192 mbits/s 1 1 reserved preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 114 lucent technologies inc. lucent technologies inc. name description tce transmitter clock edge (frm_pr47 bit 6). tce = 0 (or 1), tchidata is clocked on the falling (or rising) edge of tchick. rce receiver clock edge (frm_pr48 bit 6). rce = 0 (or 1), rchidata is latched on the falling (or rising) edge of rchick. ttse31ttse0 transmit time-slot enable 310 (frm_pr49frm_pr52). these bits define which transmit chi time slots are enabled. a 1 enables the tchidata or tchidatab time slot. a 0 forces the chi transmit highway time slot to be 3-stated. rtse31rtse0 receive time-slot enable 310 (frm_pr53frm_pr56). these bits define which receive chi time slots are enabled. a 1 enables the rchidata or rchdatab time slots. a 0 disables the time slot and transmits the programmable idle code of reg- ister frm_pr22 to the line interface. ths31ths0 transmit highway select 310 (frm_pr57frm_pr60). these bits define which transmit chi highway, tchidata or tchidatab, contains valid data for the active time slot. a 0 enables tchidata; a 1 enables the tchidatab. rhs31rhs0 receive highway select 310 (frm_pr61frm_pr64). these bits define which receive chi highway, rchidata or rchidatab, contains valid data for the active time slot. a 0 enables rchidata; a 1 enables the rchidatab. toff2toff0 transmitter bit offset (frm_pr46 bit 0bit 2). these bits are used in conjunction with the transmitter byte offset to define the beginning of the transmit frame. they determine the offset relative to tchifs, for the first bit of transmit time slot 0. the off- set is the number of tchick cycles by which the first bit is delayed. roff2roff0 receiver bit offset (frm_pr46 bit 4bit 6). these bits are used in conjunction with the receiver byte offset to define the beginning of the receiver frame. they deter- mine the offset relative to the rchifs, for the first bit of receive time slot 0. the offset is the number of rchick cycles by which the first bit is delayed. tbyoff6tbyoff0 transmitter byte offset (frm_pr47 bit 0bit 5 and frm_pr65 bit 0). these bits determine the offset from the tchifs to the beginning of the next frame on the trans- mit highway. note that in the asm mode, a frame consists of 64 contiguous bytes; whereas in other modes, a frame contains 32 contiguous bytes. allowable offsets: 2.048 mbits/s 031 bytes. 4.096 mbits/s 063 bytes. 8.192 mbits/s 0127 bytes. rbyoff6rbyoff0 receiver byte offset (frm_pr48 bit 0bit 5 and frm_pr66 bit 0). these bits determine the offset from rchifs to the beginning of the receive chi frame. note that in the asm mode, a frame consists of 64 contiguous bytes; whereas in other modes, a frame contains 32 contiguous bytes. allowable offsets: 2.048 mbits/s 031 bytes. 4.096 mbits/s 063 bytes. 8.192 mbits/s 0127 bytes. asm associated signaling mode (frm_pr44 bit 2). when enabled, the associate sig- naling mode configures the chi to carry both payload data and its associated signal- ing information. enabling this mode must be in conjunction with the programming of the chi data rate to either 4.048 mbits/s or 8.096 mbits/s. each time slot consists of 16 bits where 8 bits are data and the remaining 8 bits are signaling information. sts0sts2 stuffed time slots (frm_pr43 bit 0bit 2). valid only in t1 framing formats, these 3 bits define the location of the eight stuffed chi (unused) time slots. concentration highway interface (continued) table 57. summary of the T7630s concentration highway interface parameters (continued) lucent technologies inc. 115 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. concentration highway interface (continued) chi frame timing chi timing with chidts disabled figure 50 illustrates the chi frame timing when chidts is disabled (registers frm_pr65 bit 1 (tchidts) and frm_pr66 bit 1 (rchdts) = 0) and the chi is not in the associated signaling mode (frm_pr44 bit 2 (asm) = 0). the frames are 125 m s long and consist of 32 contiguous time slots. in ds1 frame modes, the chi frame consists of 24 payload time slots and eight stuffed (unused) time slots. in cept frame modes, the chi frame consists of 32 payload time slots. 5-5269(f).ar.2 * the position of the stuffed time is controlled by register frm_pr43 bit 0bit 2. figure 50. nominal concentration highway interface timing (for frm_pr43 bit 0bit 2 = 100 (binary)) chifs 125 m s tchidata frame 1 frame 1 frame 2 rchidata frame 2 8.192 mbits/s chi: frame 1 frame 2 rchidata 4.096 mbits/s chi: 2.048 mbits/s chi: tchidata frame 1 frame 2 high impedance high impedance 24 valid time slots high impedance frame 2 tchidata frame 2 rchidata ds1 format frame 1 frame 2 2.048 mbits/s chi: rchidata tchidata or cept format 32 valid time slots 24 valid time slots 8 stuffed slots* frame 1 preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 116 lucent technologies inc. lucent technologies inc. concentration highway interface (continued) chi timing with chidts enabled figure 51 illustrates the chi frame timing when chidts is enabled (registers frm_pr65 bit 1 (tchidts) and frm_pr66 bit 1 (rchidts) = 1) and asm is disabled (register frm_pr44 bit 2 (asm) = 0). in the chidts mode, valid chi payload time slots are alternated with high-impedance intervals of one time-slot duration. this mode is valid only for 4.096 mbits/s and 8.192 mbits/s chi rates. 5-6454(f)r.3 figure 51. chidts mode concentration highway interface timing chifs 125 m s tchidata ts0 rchidata 8.192 mbits/s chi rchidata 4.096 mbits/s chi tchidata high impedance ts1 ts2 ts3 ts0 ts1 ts2 ts3 ts31 ts0 ts31 ts0 frame 1 time slot 8 bits time slot frame 2 ts0 ts1 ts31 ts31 ts0 ts0 ts1 ts0 ts4 ts30 ts4 t30 ts2 ts30 ts2 ts30 lucent technologies inc. 117 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. concentration highway interface (continued) chi timing with associated signaling mode enabled figure 52 illustrates the chi frame timing when the associated signaling mode is enabled (register frm_pr44 bit 2 (asm) = 1) and the chidts mode is disabled (registers frm_pr65 bit 1 (tchidts) = 0 and frm_pr66 bit 1 (rchdts) = 0). the frames are 125 m s long and consist of 32 contiguous 16-bit time slots. in ds1 frame formats, each frame consists of 24 time slots and eight stuffed time slots. each time slot consists of two octets. in cept modes, each frame consists of 32 time slots. each time slot consists of two octets. 5-5270(f).ar.3 figure 52. associated signaling mode concentration highway interface timing chi timing with associated signaling mode and chidts enabled figure 53 illustrates the chi frame timing in the associated signaling mode (register frm_pr44 bit 2 (asm) = 1) and chidts enabled (registers frm_pr65 bit 1 (tchidts) = 1 and frm_pr66 bit 1 (rchidts) = 1). 5-6454(f).ar.2 * high-impedance state for tchidata and not received (dont care) for rchidata. figure 53. chi timing with asm and chidts enabled chifs 125 m s frame 1 frame 2 8.192 mbits/s chi: rchidata 4.096 mbits/s chi: tchidata frame 1 frame 1 frame 2 frame 2 high impedance rchidata tchidata or frame = 64 bytes: 32 data + 32 signaling data and signaling bytes are interleaved signaling 0 data 0 signaling 31 data 0 data 31 frame data signaling ts0 ts1 ts31 ts0 16 bits 1 time slot 16 bits 1 time slot 8.192 mbits/s chi with asm (associated signaling mode) enabled data signaling tchidata or rchidata * * * preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 118 lucent technologies inc. lucent technologies inc. concentration highway interface (continued) chi offset programming to facilitate bit offset programming, two additional internal parameters are introduced: cex is defined as the clock edge with which the first bit of time slot 0 is transmitted; cer is defined as the clock edge on which bit 0 of time slot 0 is latched. cex and cer are counted relative to the edge on which the chifs signal is sampled. values of cex and cer depend upon the values of the parameters described above. the following table gives decimal values of cex and cer for various values of tfe, rfe, tce, rce, toff[2:0], and roff[2:0]. the byte (time slot) offsets are assumed to be zero in the following examples. table 58. programming values for toff[2:0] and roff[2:0] when cms = 0 figure 54 shows an example of the relative timing of chi 2.048 mbits/s data with the following parameters: n cms = 0, tfe, rfe = 0 n tce = 1, toff[2:0] = 000, tbyoff[6:0] = 0000000 n rce = 0, roff[2:0] = 000, rbyoff[6:0] = 0000000 5-2202(f).cr.1 figure 54. tchidata and rchidata to chick relationship with cms = 0 (cex = 3 and cer = 4, respectively) rfe/ tfe rce/ tce roff[2:0] or toff[2:0] 000 001 010 011 100 101 110 111 cer or cex (decimal) 00 4681012141618 0 1 3 5 7 9 11 13 15 17 1 0 3 5 7 9 11 13 15 17 11 4681012141618 chifs is sampled on this edge: fe = 0 1 2 3 4 5 6 7 8 bit 0, ts 0 bit 1, ts 0 bit 2, ts 0 cex = 3 cer = 4 bit 0, ts 0 bit 1, ts 0 bit 2, ts 0 high impedance rchidata: rce = 0 tchidata: tce = 1 tchifs, rchifs chick lucent technologies inc. 119 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. concentration highway interface (continued) figures 55 and 56 illustrate the chi timing. 5-3916(f).cr.1 note: for case illustrated, rfe = 0, and rce = 0. figure 55. receive chi (rchidata) timing 5-3917(f).c note: for case illustrated, tfe = 0 and tce = 0. figure 56. transmit chi (tchidata) timing rchiclk rchifs rchidata t14s t14h t14s: rchifs setup = 30 ns min t15h t14h: rchifs hold = 45 ns min t15s: rchidata setup = 25 ns min t15s t15s: rchidata hold = 25 ns min tchiclk tchifs tchidata t14s t14h t14s: tchifs setup = 35 ns min t19 t14h: tchifs hold = 45 ns min t19: tchick to tchidata delay = 25 ns max preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 120 lucent technologies inc. lucent technologies inc. jtag boundary-scan specification principle of the boundary scan the boundary scan (bs) is a test aid for chip, module, and system testing. the key aspects of bs are as follows: n testing the connections between ics on a particular board. n observation of signals to the ic pins during normal operating functions. n controlling the built-in self-test (bist) of an ic. T7630 does not support bs-bist. designed according to the ieee * std. 1149.1-1990 standard, the bs test logic consists of a defined interface: the test access port (tap). the tap is made up of four signal pins assigned solely for test purposes. the fifth test pin ensures that the test logic is initialized asynchronously. the bs test logic also comprises a 16-state tap controller, an instruction register with a decoder, and several test data registers (bs register, bypass register, and dcode register). the main component is the bs register that links all the chip pins to a shift register by means of special logic cells. the test logic is designed in such a way that it is operated independently of the application logic of the T7630 (the mode multiplexer of the bs output cells may be shared). figure 57 illustrates the block diagram of the T7630s bs test logic. 5-3923(f)r.4 figure 57. block diagram of the T7630's boundary-scan test logic * ieee is a registered trademark of the institute of electrical and electronics engineers, inc. boundary-scan register tdi trst tms tck tap controller instruction decoder out tdo in mux chip kernel (unaffected by boundary-scan test) idcode register bypass register instruction register lucent technologies inc. 121 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. jtag boundary-scan specification (continued) test access port controller the test access port controller is a synchronous sequence controller with 16 states. the state changes are preset by the tms, tck, and trst signals and by the previous state. the state change always take place when the tck edge rises. figure 58 shows the tap controller state diagram. 5-3924(f)r.8 figure 58. bs tap controller state diagram the value shown next to each state transition in figure 58 represents the signal present at tms at the time of a ris- ing edge at tck. the description of the tap controller states is given in ieee std. 1149.1-1990 section 5.1.2 and is reproduced in tables 59 and 60. select-dr capture-dr 1 0 0 1 1 shift-dr exit1-dr pau s e - d r 0 1 exit2-dr update-dr 1 10 0 0 0 test logic reset run test/ idle 1 0 select-ir capture-ir 1 0 0 1 1 shift-ir exit1-ir pause-ir 0 1 exit2-ir update-ir 1 10 0 0 0 trst = 0 0 1 1 preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 122 lucent technologies inc. lucent technologies inc. jtag boundary-scan specification (continued) table 59. tap controller states in the data register branch table 60. tap controller states in the instruction register branch name description test logic reset the bs logic is switched in such a way that normal operation of the asic is adjusted. the idcode instruction is initialized by test logic reset. irre- spective of the initial state, the tap controller has achieved test logic reset after five control pulses at the latest when tms = 1. the tap controller then remains in this state. this state is also achieved when trst = 0. run test/idle using the appropriate instructions, this state can activate circuit parts or initiate a test. all of the registers remain in their present state if other instructions are used. select dr this state is used for branching to the test data register control. capture dr the test data is loaded in the test data register parallel to the rising edge of tck in this state. shift dr the test data is clocked by the test data register serially to the rising edge of tck in the state. the tdo output driver is active. exit (1/2) dr this temporary state causes a branch to a subsequent state. pause dr the input and output of test data can be interrupted in this state. update dr the test data is clocked into the second stage of the test data register parallel to the falling edge of tck in this state. name description select ir this state is used for branching to the instruction register control. capture ir the instruction code 0001 is loaded in the first stage of the instruction register parallel to the rising edge of tck in this state. shift ir the instructions are clocked into the instruction register serially to the rising edge of tck in the state. the tdo output driver is active. exit (1/2) ir this temporary state causes a branch to a subsequent state. pause ir the input and output of instructions can be interrupted in this state. update ir the instruction is clocked into the second stage of the instruction register parallel to the falling edge of tck in this state. lucent technologies inc. 123 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) lucent technologies inc. jtag boundary-scan specification (continued) instruction register the instruction register (ir) is 4 bits in length. table 61 shows the bs instructions implemented by the T7630. table 61. T7630s boundary-scan instructions instruction code act. register tdi tdo mode function output defined via extest 0000 boundary scan test test external connections bs register idcode 0001 identification normal read manuf. register core logic highz 0100 bypass x 3-state outputhigh impedance sample/preload 0101 boundary scan normal sample/load core logic bypass 1111 bypass normal min. shift path core logic everything else bypass x outputhigh impedance the instructions not supported in T7630 are intest, runbist, and toggle. a fixed binary 0001 pattern (the 1 into the least significant bit) is loaded into the ir in the capture-ir controller state. the idcode instruc- tion (binary 0001) is loaded into the ir during the test- logic-reset controller state and at powerup. the following is an explanation of the instructions sup- ported by T7630 and their effect on the devices' pins. extest this instruction enables the path cells, the pins of the ics, and the connections between asics to be tested via the circuit board. the test data can be loaded in the chosen position of the bs register by means of the sample/preload instruction. the extest instruc- tion selects the bs register as the test data register. the data at the function inputs is clocked into the bs register on the rising edge of tck in the capture-dr state. the contents of the bs register can be clocked out via tdo in the shift-dr state. the value of the function outputs is solely determined by the contents of the data clocked into the bs register and only changes in the update-dr state on the falling edge of tck. idcode information regarding the manufacturers id for lucent, the ic number, and the version number can be read out serially by means of the idcode instruction. the idcode register is selected, and the bs register is set to normal mode in the update-ir state. the idcode is loaded at the rising edge of tck in the capture- dr state. the idcode register is read out via tdo in the shift-dr state. highz all 3-statable outputs are forced to a high-impedance state, and all bidirectional ports to an input state by means of the highz instruction. the impedance of the outputs is set to high in the update-ir state. the func- tion outputs are only determined in accordance with another instruction if a different instruction becomes active in the update-ir state. the bypass register is selected as the test data register. the highz instruc- tion is implemented in a similar manner to that used for the bypass instruction. sample/preload the sample/preload instruction enables all the inputs and outputs pins to be sampled during operation (sample) and the result to be output via the shift chain. this instruction does not impair the internal logic functions. defined values can be serially loaded in the bs cells via tdi while the data is being output (pre- load). preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 124 lucent technologies inc. lucent technologies inc. jtag boundary-scan specification (continued) bypass this instruction selects the bypass register. a minimal shift path exists between tdi and tdo. the bypass reg- ister is selected after the update-ir. the bs register is in normal mode. a 0 is clocked into the bypass register during capture-dr state. data can be shifted by the bypass register during shift-dr. the contents of the bs register do not change in the update-dr state. please note that a 0 that was loaded during capture-dr appears first when the data is being read out. boundary-scan register the boundary-scan register is a shift register, whereby one or more bs cells are assigned to every digital T7630 pin (with the exception of the pins for the bs architecture, analog signals, and supply voltages). the T7630s boundary-scan register bit-to-pin assignment is to be determined. bypass register the bypass register is a one-stage, shift register that enables the shift chain to be reduced to one stage in the T7630. idcode register the idcode register identifies the T7630 by means of a parallel, loadable, 32-bit shift register. the code is loaded on the rising edge of tck in the capture-dr state. the 32-bit data is organized into four sections as follows. table 62. idcode register 3-state procedures the 3-state input participates in the boundary scan. it has a bs cell, but buffer blocking via this input is suppressed for the extest instruction. the 3-state input is regarded as a signal input that is to participate in the connection test during extest. the buffer blocking function should not be active during extest to ensure that the update pattern at the T7630 outputs does not become corrupted. version part number manufacturer id 1 bits 3128 bits 2712 bits 111 bit 0 0001 0111 011000110000 0000 0011101 1 lucent technologies inc. 125 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. microprocessor interface overview the T7630 device is equipped with a microprocessor interface that can operate with most commercially avail- able microprocessors. the microprocessor interface provides access to all the internal registers through a 12-bit address bus and an 8-bit data bus. inputs mpmode and mpmux (pins 74 and 76) are used to configure this interface into one of four possible modes, as shown in table 63. the mpmux setting selects either a multiplexed (8-bit address/data bus, ad[7:0]) or a demultiplexed (12-bit address bus, a[11:0] and an 8-bit data bus ad[7:0]) mode of operation. the mpmode setting selects the associated set of control signals required to access a set of registers within the device. the microprocessor interface can operate at speeds up to 33 mhz in interrupt-driven or polled mode without requiring any wait-states. for microprocessors operat- ing at greater than 33 mhz, the rdy_dtack output (pin 100) may be used to introduce wait-states in the read/write cycles. in the interrupt-driven mode, one or more device alarms will assert the interrupt output (pin 99) once per alarm activation. after the microprocessor identifies the source(s) of the alarm(s) (by reading the global interrupt register) and reads the specific alarm status registers, the interrupt output will deassert. in the polled mode, however, the microprocessor monitors the various device alarm status by periodically reading the alarm status registers within the line interface unit, framer, and hdlc blocks without the use of inter- rupt. in both interrupt and polled methods of alarm servicing, the status registers within an identified block will clear on a microprocessor read cycle only when the alarm condition within that block no longer exists; oth- erwise, the alarm status register bit remains set. the powerup default states for the line interface unit, framer, and the hdlc blocks are discussed in their respective sections. all read/write registers within these blocks must be written by the microprocessor on system start-up to guarantee proper device functional- ity. register addresses not defined in this data sheet must not be written. details concerning the microprocessor interface con- figuration modes, pinout definitions, clock specifica- tions, register address map, i/o timing specifications, and the i/o timing diagrams are described in the follow- ing sections. microprocessor configuration modes table 63 highlights the four microprocessor modes controlled by the mpmux and mpmode inputs (pins 76 and 74). table 63. microprocessor configuration modes * ale _as may be connected to ground in this mode. ? the dtack signal is asynchronous to the mpclk signal. mode mpmode mpmux address/data bus generic control, data, and output pin names mode 1 0 0 demuxed* cs , as , ds , r/ w , a[11:0], ad[7:0], int, dtack ? mode 2 0 1 muxed cs , as , ds , r /w , a[11:8], ad[7:0], int, dtac k ? mode 3 1 0 demuxed* cs , a le , rd , wr , a[11:0], ad[7:0], int, rdy mode 4 1 1 muxed cs , ale , rd , wr , a[11:8], ad[7:0], int, rdy preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 126 lucent technologies inc. lucent technologies inc. microprocessor interface (continued) microprocessor interface pinout definitions the mode [14] specific pin definitions are given in table 64. note that the microprocessor interface uses the same set of pins in all modes. table 64. mode [14] microprocessor pin definitions * interrupt output is synchronous to the internal clock source rlck-liu. if rlck_liu is absent, the reference clock for interrup t timing becomes an interval 2.048 mhz clock derived from the chi clock. ? the dtack output is asynchronous to mpclk. ? mpclk is needed if rdy output is required to be synchronous to mpclk. in the default (reset) mode, interrupt is active-high. it can be made active-low by setting register greg4 bit 6 to 1. configuration pin number device pin name generic pin name pin_type assertion sense function mode 1 107 wr _ds ds input active-low data strobe 75 rd _r/w r/w input read/write r/w = 1 => read r/w = 0 => write 77 ale _as as input active-low address strobe 78 cs cs input active-low chip select 99 interrupt interrupt * output active-high/ low interrupt 100 rdy_dtack dtack ? output active-low data acknowledge 8679 ad[7:0] ad[7:0] i/o data bus 9887 a[11:0] a[11:0] input address bus 101 mpclk mpclk input microprocessor clock mode 2 107 wr _ds ds input active-low data strobe 75 rd _r/w r/w input read/write r/w = 1 => read r/w = 0 => write 77 ale _as as input address strobe 78 cs cs input active-low chip select 99 interrupt interrupt * output active-high/low interrupt 100 rdy_dtack dtack ? output active-low data acknowledge 8679 ad[7:0] ad[7:0] i/o address/data bus 9887 a[11:8], ad[7:0] a[11:8], ad[7:0] input address/data bus 101 mpclk mpclk input microprocessor clock mode 3 107 wr _ds wr input active-low write 75 rd _r/w rd input active-low read 77 ale _as ale input active-low address latch enable 78 cs cs input active-low chip select 99 interrupt interrupt * output active-high/low interrupt 100 rdy_dtack rdy ? output active-high ready 8679 ad[7:0] ad[7:0] i/o data bus 9887 a[11:0] a[11:0] input address bus 101 mpclk mpclk input microprocessor clock mode 4 107 wr _ds wr input active-low write 75 rd _r/w rd input active-low read 77 ale _as ale input address latch enable 78 cs cs input active-low chip select 99 interrupt interrupt * output active-high/low interrupt 100 rdy_dtack rdy ? output active-high ready 8679 ad[7:0] ad[7:0] i/o address/data bus 9887 a[11:8], ad[7:0] a[11:8], ad[7:0] input address/data bus 101 mpclk mpclk input microprocessor clock lucent technologies inc. 127 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. microprocessor interface (continued) microprocessor clock (mpclk) specifications the microprocessor interface is designed to operate at clock speeds up to 33 mhz without requiring any wait- states. wait-states may be needed if higher microprocessor clock speeds are required. the microprocessor clock (mpclk, pin 101) specification is shown in table 65. this clock must be supplied only if the rdy (mode 3 and mode 4) is required to be synchronous to mpclk. table 65. microprocessor input clock specifications microprocessor interface register address map the register address space is divided into eight contiguous banks of 512 addressable units each. each address- able unit is an 8-bit register. these register banks are labeled as regbank[7:0]. the register address map table gives the address range of these register banks and their associated circuit blocks. regbank0 contains the global registers which are common to all the circuit blocks on T7630. regbank1 is reserved and must not be written. regbank[2, 5] are attached to the liu circuit blocks. regbank[3, 6] are attached to the framer circuit blocks. regbank[4, 7] are attached to the fdl circuit blocks. the descriptions of the individual register banks can be found in the appropriate sections of this document. in these descriptions, all addresses are given in hexadecimal. addresses out of the range specified by table 66 must not be addressed. if they are written, they must be written to 0. an inadvertant write to an out-of-range address may be corrected by a device reset. table 66. T7630 register address map * core registers are common to all circuit blocks on T7630. i/o timing the i/o timing specifications for the microprocessor interface are given in table 67. the microprocessor interface pins are compatible with cmos/ttl i/o levels. all outputs, except the address/data bus ad[7:0], are rated for a capacitive load of 50 pf. the ad[7:0] outputs are rated for a 100 pf load. name symbol period and toler ance t rise typ t fall typ duty cycle unit min high min low mpclk t1 30 to 323 2 2 12 12 ns register bank label start address (in hex) end address (in hex) circuit block name regbank0 000 007 T7630 global registers * regbank1 reserved regbank2 400 406 line interface unit 1 (liu1) regbank3 600, 6e0 6a6, 6ff framer1 regbank4 800 80e facility data link 1 (fdl1) regbank5 a00 a06 line interface unit 2 (liu2) regbank6 c00, ce0 ca6, cff framer2 regbank7 e00 e0e facility data link 2 (fdl2) preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 128 lucent technologies inc. lucent technologies inc. microprocessor interface (continued) in modes 1 and 3, asserting ale _as signal low is used to enable the internal address bus. in modes 2 and 4, the falling edge of ale _as signal is used to latch the address bus. table 67. microprocessor interface i/o timing specifications symbol configuration parameter setup (ns) (min) hold (ns) (min) delay (ns) (max) t1 modes 1 & 2 as asserted width 10 t2 address valid to as deasserted 10 t3 as deasserted to address invalid 10 t4 t5 r/w valid to both cs and ds asserted 4 t6 address valid and as asserted to ds asserted (read) 0 t7 cs asserted to dtack low impedance 12 t8 ds asserted to dtack asserted 15 t9 ds asserted to ad low impedance (read) 15 t10 dtack asserted to data valid 25 t11 ds deasserted to cs deasserted (read) 5 t12 ds deasserted to r/w invalid 5 t13 ds deasserted to dtack deasserted 12 t14 cs deasserted to dtack high impedance 10 t15 ds deasserted to data invalid (read) 5 t16 address valid and as asserted to ds asserted (write) 10 t17 data valid to ds asserted 10 t18 ds deasserted to cs deasserted (write) 5 t19 ds deasserted to data valid 10 t20 ds asserted width (write) 10 t21 address valid to as falling edge 10 t22 as falling edge to address invalid 10 t23 as falling edge to ds asserted (read) 0 t24 as falling edge to ds asserted (write) 10 t25 cs asserted to ds asserted (write) 10 lucent technologies inc. 129 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. microprocessor interface (continued) table 67. microprocessor interface i/o timing specifications (continued) note: the read and write timing diagrams for all four microprocessor interface modes are shown in figure 59figure 66. symbol configuration parameter setup (ns) (min) hold (ns) (min) delay (ns) (max) t31 modes 3 & 4 ale asserted width 10 t32 address valid to ale deasserted 10 t33 ale deasserted to address invalid 10 t34 cs asserted to rd asserted 0 t35 address valid and ale asserted to rd asserted 0 t36 cs asserted to rdy low impedance 12 t37 rising edge mpck to rdy asserted 15 t38 rd asserted to ad low impedance 15 t39 rd asserted to data valid 40 t40 rd deasserted to cs deasserted 5 t41 rd deasserted to rdy deasserted 15 t42 cs deasserted to rdy high impedance 10 t43 rd deasserted to data invalid (high impedance) 5 t44 cs asserted to wr asserted 0 t45 address valid and ale asserted to wr asserted 10 t46 data valid to wr asserted 10 t47 wr deasserted to cs deasserted 5 t48 wr deasserted to rdy deasserted 15 t49 wr deasserted to data invalid 10 t50 rd asserted width 50 t51 wr asserted width 10 t52 address valid to ale falling edge 10 t53 ale falling edge to address invalid 10 t54 ale falling edge to rd asserted 0 t55 ale falling edge to wr asserted 10 preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 130 lucent technologies inc. lucent technologies inc. microprocessor interface (continued) 5-6422(f)r.1 figure 59. mode 1read cycle timing (mpmode = 0, mpmux = 0) 5-6423(f) figure 60. mode 1write cycle timing (mpmode = 0, mpmux = 0) ad[0:7] dtack ds r/w a[0:11] as cs t1 t2 t3 valid address t5 t6 t7 t8 t10 t9 valid data t13 t15 t14 t12 t11 ad[0:7] dtack ds r/w a[0:11] as cs t1 t2 t3 valid address t16 t25 t7 t8 t17 valid data t13 t19 t14 t12 t18 t5 t20 lucent technologies inc. 131 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. microprocessor interface (continued) 5-6424(f) figure 61. mode 2read cycle timing (mpmode = 0, mpmux = 1) 5-6425(f) figure 62. mode 2write cycle timing (mpmode = 0, mpmux = 1) ad[0:7] dtack ds r/w a[8:11] as cs t1 t21 t22 valid address t5 t23 t7 t8 t10 t9 valid data t13 t15 t14 t12 t11 valid address t21 t22 ad[0:7] dtack ds r/w a[8:11] as cs t1 t21 t22 valid address t5 t24 t7 t8 t17 valid data t13 t19 t14 t12 t18 valid address t21 t22 t25 t20 preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 132 lucent technologies inc. lucent technologies inc. microprocessor interface (continued) 5-6426(f)r.1 figure 63. mode 3read cycle timing (mpmode = 1, mpmux = 0) 5-6427(f) figure 64. mode 3write cycle timing (mpmode = 1, mpmux = 0) mpck ad[0:7] rdy rd a[0:11] ale cs t31 t32 t33 valid address t34 t50 t35 valid data t42 t41 t37 t36 t40 t39 t38 t43 mpck ad[0:7] rdy wr a[0:11] ale cs t31 t32 t33 valid address t44 t51 t45 valid data t42 t37 t36 t47 t46 t48 t49 lucent technologies inc. 133 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. microprocessor interface (continued) 5-6428(f)r.1 figure 65. mode 4read cycle timing (mpmode = 1, mpmux = 1) 5-6429(f)r.1 figure 66. mode 4write cycle timing (mpmode = 1, mpmux = 1) mpck ad rdy rd a[8:11] ale cs t31 valid address valid data t52 t53 t34 t54 t36 t37 t39 t38 valid address t52 t53 t43 t41 t42 t40 t50 mpck ad rdy wr a[8:11] ale cs t31 valid address valid data t52 t53 t44 t55 t36 t37 valid address t52 t53 t49 t48 t42 t47 t51 t46 preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 134 lucent technologies inc. lucent technologies inc. reset both hardware and software resets are provided. hardware reset (pin 43/139) hardware reset is enabled by asserting reset to 0. each channel has independent resets, reset1 (pin 139) for channel 1 and reset2 (pin 43) for channel 2. the device is in an inactive condition when reset is 0, and becomes active when reset is returned to 1. eight cycles of the liu receive line clock, i.e., 5.2 s for t1 or 3.9 s for e1, is required to guarantee a complete reset. upon completion of a reset cycle, the liu regis- ter default values are controlled by the setting of ds1/cept (pin 40/142), as given in table 7. transmit line interface short-haul equalizer/rate control. if ds1/cept is 1, the defaults are set for ds1 with line equalization for a 1 ft. to 131 ft. span. if ds1/cept is 0, the defaults are set for cept with a line equalization for 120 w twisted pair or 75 w coax option 1. hardware reset of a single channel returns all liu, framer, and fdl registers of that channel to their default values, as listed in the individual register descriptions and register maps, table 197table 202. reset of a single channel does not reset the global reg- isters. hardware reset of both channels simultaneously, both pin 43 and pin 139 set to 0, results in a complete device reset including a reset of the global registers. software reset/software restart independent software reset for each functional block of the device is available. the liu may be placed in restart through register liu_reg2 bit 5 (restart). the framer may be reset through register frm_pr26 bit 0 (swreset), or placed in restart through frm_pr26 bit 1 (swrestart). the fdl receiver may be reset through register fdl_pr26 bit 1 (frr), and the fdl transmitter may be reset through fdl_pr1 bit 5 (ftr). the reset functions, framer swreset (framer software reset), fdl frr (fdl receiver reset), and ftr (fdl transmitter reset), reset the block and return all parameter/control registers for the block to their default values. the restart functions, liu restart and framer swrestart (framer soft- ware restart), reset the block but do not alter the value of the parameter/control registers. lucent technologies inc. 135 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. register architecture table 68 is an overview of the register architecture. the table is a summary of the register function and address. complete detail of each register is given in the following sections. table 68. register summary register function register address (hex) channel 1 channel 2 global registers greg0 primary block interrupt status 000 greg1 primary block interrupt enable 001 greg2 global loopback control 002 greg3 global loopback control 003 greg4 global control 004 greg5 device id and version 005 greg6 device id and version 006 greg7 device id and version 007 liu registers liu_reg0 liu alarm status 400 a00 liu_reg1 liu alarm interrupt enable 401 a01 liu_reg2 liu control 402 a02 liu_reg3 liu control 403 a03 liu_reg4 liu control 404 a04 liu_reg5 liu configuration 405 a05 liu_reg6 liu configuration 406 a06 framer registers status registers frm_sr0 interrupt status 600 c00 frm_sr1 facility alarm condition 601 c01 frm_sr2 remote end alarm 602 c02 frm_sr3 facility errored event 603 c03 frm_sr4 facility event 604 c04 frm_sr5 exchange termination and exchange termination remote end interface status 605 c05 frm_sr6 network termination and network termination remote end inter- face status 606 c06 frm_sr7 facility event 607 c07 frm_sr8, frm_sr9 bipolar violation counter 608, 609 c08, c09 frm_sr10, frm_sr11 framing bit error counter 60a, 60b c0a, c0b frm_sr12, frm_sr13 crc error counter 60c, 60d c0c, c0d frm_sr14, frm_sr15 e-bit counter 60e, 60f c0e, c0f preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 136 lucent technologies inc. lucent technologies inc. register architecture (continued) table 68. register summary (continued) register function register address (hex) channel 1 channel 2 framer registers (continued) status registers (continued) frm_sr16, frm_sr17 crc-4 error at nt1 from nt2 counter 610, 611 c10, c11 frm_sr18, frm_sr19 e-bit at nt1 from nt2 counter 612, 613 c12, c13 frm_sr20, frm_sr21 et errored seconds counter 614, 615 c14, c15 frm_sr22, frm_sr23 et bursty errored seconds counter 616, 617 c16, c17 frm_sr24, frm_sr25 et severely errored seconds counter 618, 619 c18, c19 frm_sr26, frm_sr27 et unavailable seconds counter 61a, 61b c1a, c1b frm_sr28, frm_sr29 et-re errored seconds counter 61c, 61d c1c, c1d frm_sr30, frm_sr31 et-re bursty errored seconds counter 61e, 61f c1e, c1f frm_sr32, frm_sr33 et-re severely errored seconds counter 620, 621 c20, c21 frm_sr34, frm_sr35 et-re unavailable seconds counter 622, 623 c22, c23 frm_sr36, frm_sr37 nt1 errored seconds counter 624, 625 c24, c25 frm_sr38, frm_sr39 nt1 bursty errored seconds counter 626, 627 c26, c27 frm_sr40, frm_sr41 nt1 severely errored seconds counter 628, 629 c28, c29 frm_sr42, frm_sr43 nt1 unavailable seconds counter 62a, 62b c2a, c2b frm_sr44, frm_sr45 nt1-re errored seconds counter 62c, 62d c2c, c2d frm_sr46, frm_sr47 nt1-re bursty errored seconds counter 62e, 62f c2e, c2f frm_sr48, frm_sr49 nt1-re severely errored seconds counter 630, 631 c30, c31 frm_sr50, frm_sr51 nt1-re unavailable seconds counter 632, 633 c32, c33 frm_sr52 receive not-fas ts0 634 c34 frm_sr53 received sa 635 c35 frm_sr54 frm_sr63 slc -96 fdl/cept sa receive stack 63663f c36c3f lucent technologies inc. 137 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. register architecture (continued) table 68. register summary (continued) register function register address (hex) channel 1 channel 2 framer registers (continued) received signaling registers frm_rsr0 frm_rsr31 received signaling 64065f c40c5f parameter/control registers frm_pr0 frm_pr7 interrupt group enable 660667 c60c67 frm_pr8 framer mode option 668 c68 frm_pr9 framer crc control option 669 c69 frm_pr10 alarm filter 66a c6a frm_pr11 errored second threshold 66b c6b frm_pr12, frm_pr13 severely errored second threshold 66c. 66d c6c, c6d frm_pr14 errored event enable 66e c6e frm_pr15 et remote end errored event enable 66f c6f frm_pr16 nt1 errored event enable 670 c70 frm_pr17, frm_pr18 nt1 remote end errored event enable 671, 672 c71, c72 frm_pr19 automatic ais to the system and automatic loopback enable 673 c73 frm_pr20 transmit to the line command 674 c74 frm_pr21 framer fdl loopback transmission codes command 675 c75 frm_pr22 framer transmit line idle code 676 c76 frm_pr23 framer transmit system idle code 677 c77 frm_pr24 primary loopback control 678 c78 frm_pr25 secondary loopback control 679 c79 frm_pr26 system frame sync mask source 67a c7a frm_pr27 transmission of remote frame alarm and cept automatic transmission of a bit = 1 control 67b c7b frm_pr28 cept automatic transmission of e bit = 0 67c c7c frm_pr29 sa4sa8 source 67d c7d frm_pr30 sa4sa8 control 67e c7e frm_pr31 frm_pr40 sa transmit stack/ slc -96 transmit stack 67f688 c7fc88 frm_pr41 si-bit source 689 c89 frm_pr42 frame exercise 68a c8a frm_pr43 system interface control 68b c8b frm_pr44 signaling mode 68c c8c frm_pr45 chi common control 68d c8d frm_pr46 chi common control 68e c8e frm_pr47 chi transmit control 68f c8f frm_pr48 chi receive control 690 c90 preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 138 lucent technologies inc. lucent technologies inc. register architecture (continued) table 68. register summary (continued) register function register address (hex) channel 1 channel 2 framer registers (continued) parameter/control registers (continued) frm_pr49 frm_pr52 transmit chi time-slot enable 691694 c91c94 frm_pr53 frm_pr56 receive chi time-sot enable 695698 c95c98 frm_pr57 frm_pr60 chi transmit highway select 69969c c99c9c frm_pr61 frm_pr64 chi receive highway select 69d6a0 c9dca0 frm_pr65 chi transmit control 6a1 ca1 frm_pr66 chi receive control 6a2 ca2 frm_pr69 auxiliary pattern generator control 6a5 ca5 frm_pr70 auxiliary pattern detector control 6a6 ca6 transmit signaling registers frm_tsr0 frm_tsr31 transmit signaling 6e06f7 ce0cf7 facility data link registers fdl parameter/control registers fdl_pr0 fdl configuration control 800 e00 fdl_pr1 fdl control 801 e01 fdl_pr2 fdl interrupt mask control 802 e02 fdl_pr3 fdl transmitter configuration control 803 e03 fdl_pr4 fdl transmitter fifo 804 e04 fdl_pr5 fdl transmitter mask 805 e05 fdl_pr6 fdl receive interrupt level control 806 e06 fdl_pr7 not assigned fdl_pr8 fdl receive match character 808 e08 fdl_pr9 fdl transparent control 809 e09 fdl_pr10 fdl transmit ansi esf bit codes 80a e0a fdl status registers fdl_sr0 fdl interrupt status 80b e0b fdl_sr1 fdl transmitter status 80c e0c fdl_sr2 fdl receiver status 80d e0d fdl_sr3 fdl ansi bit codes status 80e e0e fdl_sr4 fdl receive fifo 807 e07 lucent technologies inc. 139 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. global register architecture regbank0 contains the status and programmable control registers for all global functions. the address of these registers is 000 (hex) to 007 (hex). these registers control both channels of the terminator. the register bank architecture is shown in table 69. the register bank consists of 8-bit registers classified as pri- mary block interrupt status register, primary block interrupt enable register, global loopback control register, global terminal control register, device identification register, and global internal interface control register. greg0 is a clear on read (cor) register. this register is cleared by the framer internal received line clock (liu_rlck of figure 18 block diagram of framer line interface on page 46). at least two rfrmck cycles (1.3 s for ds1 and 1.0 s for cept) must be allowed between successive reads of the same cor register to allow it to properly clear. the default values are shown in parentheses. table 69. global register set (0x0000x008) the following section describes the global registers in tables 7075. global register [address (hex)] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 greg0[000] reserved (0) fdl2int (0) frmr2int (0) liu2int (0) reserved (0) fdl1int (0) frmr1int (0) liu1int (0) greg1[001] reserved (0) fdl2ie (0) frmr2ie (0) liu2ie (0) reserved (0) fdl1ie (0) frmr1ie (0) liu1ie (0) greg2[002] tid2-rsd1 (0) tsd2-rsd1 (0) tid1-rsd1 (0) tsd1-rsd1 (0) tsd2-rid1 (0) tid2-rid1 (0) tsd1-rid1 (0) tid1-rid1 (0) greg3[003] tid1-rsd2 (0) tsd1-rsd2 (0) tid2-rsd2 (0) tsd2-rsd2 (0) tsd1-rid2 (0) tid1-rid2 (0) tsd2-rid2 (0) tid2-rid2 (0) greg4[004] reserved (0) alie (0) secctrl (0) reserved (0) t1-r2 (0) t2-r1 (0) reserved (0) reserved (0) greg5[005]0111 0110 greg6[006]0011 0000 greg7[007]0000 0010 preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 140 lucent technologies inc. lucent technologies inc. global register structure primary block interrupt status register (greg0) a bit set to 1 indicates the block has recently generated an interrupt. this register is cleared on read. table 70. primary block interrupt status register (greg0) (000) primary block interrupt enable register (greg1) this register enables the individual blocks to assert the interrupt pin. table 71. primary block interrupt enable register (greg1) (001) bit symbol description 0liu1int line interface unit 1 interrupt. a 1 indicates liu1 generated an interrupt. 1 frmr1int framer 1 interrupt. a 1 indicates framer 1 generated an interrupt. 2 fdl1int facility data link 1 interrupt. a 1 indicates fdl1 generated an interrupt. 3 reserved. 4liu2int line interface unit 2 interrupt. a 1 indicates liu2 generated an interrupt. 5 frmr2int framer 2 interrupt. a 1 indicates framer 2 generated an interrupt. 6 fdl2int facility data link 2 interrupt. a 1 indicates fdl2 generated an interrupt. 7 reserved. bit symbol description 0liu1ie line interface 1 interrupt enable. a 1 enables liu1 interrupts. 1 frmr1ie framer 1 interrupt enable. a 1 enables framer 1 interrupts. 2 fdl1ie facility data link 1 interrupt enable. a 1 enables fdl1 interrupts. 3 reserved. write to 0. 4liu2ie line interface 2 interrupt enable. a 1 enables liu2 interrupts. 5 frmr2ie framer 2 interrupt enable. a 1 enables framer 2 interrupts. 6 fdl2ie facility data link 2 interrupt enable. a 1 enables fdl2 interrupts. 7 reserved. write to 0. lucent technologies inc. 141 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. global register structure (continued) global loopback control register (greg2) this register enables the framer inputs rchidata1 and rchidatab1 to be driven by various internal sources. a 1 enables the specified loopback. the default of the register 00 (hex) disables all loopbacks and enables external sources to drive these inputs. table 72. global loopback control register (greg2) (002) global loopback control register (greg3) this register enables the framer inputs rchidata2 and rchidatab2 to be driven by various internal sources. a 1 enables the specified loopback. the default of the register 00 (hex) disables all loopbacks and enables external sources to drive these inputs. table 73. global loopback control register (greg3) (003) bit symbol description 0tid1rid1 tchidata1 to rchidata1 connection. 1 tsd1rid1 tchidatab1 to rchidata1 connection. 2tid2rid1 tchidata2 to rchidata1 connection. 3 tsd2rid1 tchidatab2 to rchidata1 connection. 4 tsd1rsd1 tchidatab1 to rchidatab1 connection. 5 tid1rsd1 tchidata1 to rchidatab1 connection. 6 tsd2rsd1 tchidatab2 to rchidatab1 connection. 7 tid2rsd1 tchidata2 to rchidatab1 connection. bit symbol description 0tid2rid2 tchidata2 to rchidata2 connection. 1 tsd2rid2 tchidatab2 to rchidata2 connection. 2tid1rid2 tchidata1 to rchidata2 connection. 3 tsd1rid2 tchidatab1 to rchidata2 connection. 4 tsd2rsd2 tchidatab2 to rchidatab2 connection. 5 tid2rsd2 tchidata2 to rchidatab2 connection. 6 tsd1rsd2 tchidatab1 to rchidatab2 connection. 7 tid1rsd2 tchidata1 to rchidatab2 connection. preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 142 lucent technologies inc. lucent technologies inc. global register structure (continued) global control register (greg4) this register enables liu1 to liu2 loopbacks (bit 2 and bit 3), source of the output second pulse (bit 5), interrupt polarity (bit 6), and source of framer resets (bit 7). table 74. global control register (greg4) (004) device id and version registers (greg5 greg7) these bits define the device and version number. table 75. device id and version registers (greg5 greg7) (005007) bit symbol description 0 reserved. write to zero. 1 reserved. write to zero. 2t2-r1 tlck2, tpd2, and tnd2 to rlck1, rpd1, and rnd1 connection. a 1 makes the indicated loopback. 3t1-r2 tlck1, tpd1, and tnd1 to rlck2, rpd2, and rnd2 connection. a 1 makes the indicated loopback. 4 reserved. write to zero. 5 secctrl second pulse source control. a 0 enables framer 1 to source the output second pulse (second). a 1 enables framer 2 to source the output second pulse. 6alie active-low interrupt enable. a 1 enables active-low interrupt. 7 reserved. write to zero. register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device code greg5 01 110110 device code greg6 00 110000 version # greg7 00 000010 lucent technologies inc. 143 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. line interface unit (liu) register architecture regbank2 and regbank5 contain the status and programmable registers for the line interface unit channels liu1 and liu2 respectively. the base address for regbank2 is 400(hex) and for regbank5 is a00(hex). within these register banks, the bit map is identical for both liu1 and liu2. the register bank architecture for liu1 and liu2 is shown in table 76. the register bank consists of 8-bit registers classified as alarm status register, alarm mask register, status register, status interrupt mask register, control regis- ters, and configuration registers. register liu_reg0 is the alarm status register used for storing the various liu alarms and status. it is a read-only, clear-on-read (cor) register. this register is cleared on the rising edge of mpclk, if present, or on the rising edge of the internally generated 2.048 mhz clock derived from the chi clock if mpclk is not present. register liu_reg1 contains the individual interrupt enable bits for the alarms in liu_reg0. register liu_reg2, liu_reg3, and liu_reg4 are designated as control registers while liu_reg5 and liu_reg6 are configuration registers. these are used to set up the individual liu channel functions and parame- ters. the default values are shown in parentheses. the following sections describe the liu registers in more detail. table 76. line interface units register set * ((40040f); (a00a0f)) * the logic value, in parentheses below each bit definition, is the default state upon completion of hardware reset. ? these bits must be written to 1. liu register liu register [address (hex)] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 alarm register (read only) (latches alarm, clear on read) liu_reg0 400; a00 0 0 0 0 lotc tdm dlos alos alarm interrupt enable register (read/write) liu_reg1 401; a01 reserved (0) reserved (0) reserved (0) reserved (0) lotcie (0) tdmie (0) dlosie (0) alosie (0) control registers (read/write) liu_reg2 402; a02 reserved (0) reserved (0) restart (0) highz (0) reserved (0) losst (0) reserved (0) reserved (0) liu_reg3 403; a03 reserved ? (1) reserved ? (1) reserved ? (1) lossd (0) dual (0) code (1) jat (0) jar (0) liu_reg4 404; a04 reserved (0) reserved (0) jabw0 (0) phizalm (0) prlalm (0) pflalm (0) rcvais (0) altimer (0) configuration registers (read/write) liu_reg5 405; a05 reserved (0) reserved (0) reserved (0) reserved (0) loopa (0) loopb (0) xlais (1) pwrdn (0) liu_reg6 406; a06 reserved (0) reserved (0) reserved (0) reserved (0) reserved 0 (0) eq2 (0,ds1) (1,cept) eq1 (0,ds1) (1,cept) eq0 (0) preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 144 lucent technologies inc. lucent technologies inc. line interface alarm register alarm status register (liu_reg0) bits 03 of this register represent the status of the line interface receiver and transmitter alarms alos, dlos, tdm, and lotc. the alarm indicators are active-high and automatically clear on a microprocessor read if the cor- responding alarm conditions no longer exist. * however, persistent alarm conditions will cause these bits to remain set even after a microprocessor read. this is a read-only register. table 77. liu alarm status register (liu_reg0) (400, a00) line interface alarm interrupt enable register alarm interrupt enable register (liu_reg1) the bits in the alarm interrupt enable register allow the user to selectively enable generation of an interrupt by each channel alarm. the enable bits correspond to their associated alarm status bits in the alarm status register, liu- reg0. the interrupt enable function is active-high. when an enable bit is set, the corresponding alarm is enabled to generate an interrupt. otherwise, the alarm is disabled from generating an interrupt. the enable function only impacts the ability to generate an interrupt signal. the proper alarm status will be reflected in liu_reg0 even when the corresponding enable bit is set to zero. any other liu behavior associated with an alarm event will operate normally even if the interrupt is not enabled. this is a read/write register table 78. liu alarm interrupt enable register (liu_reg1) (401, a01) * see T7630 device advisory for signal timing requirements. bit symbol description 0alos receive analog loss of signal. a 1 indicates the liu receive channel has detected an analog loss of signal condition/event. 1dlos receive digital loss of signal. a 1 indicates the liu receive channel has detected a digital loss of signal condition/event. 2tdm transmit driver monitor alarm. a 1 indicates the liu transmit channel has detected a transmit driver monitor alarm condition/event. 3lotc transmit loss of transmit clock alarm. a 1 indicates the liu transmit channel has detected a loss of transmit clock condition/event. 47 reserved. bit symbol description 0alosie enable analog loss of signal interrupt. a 1 enables an interrupt in response to alos alarm. 1dlosie enable digital loss of signal interrupt. a 1 enables an interrupt in response to dlos alarm. 2tdmie enable transmit driver monitor interrupt. a 1 enables an interrupt in response to tdm alarm. 3lotcie enable loss of transmit clock interrupt. a 1 enables an interrupt in response to lotc alarm. 47 reserved. write to 0. lucent technologies inc. 145 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. line interface control registers the bits in the control registers allow the user to configure the various device functions for the individual line inter- face channels 1 and 2. all the control bits (with the exception of losstd) are active-high. liu control register (liu_reg2) table 79. liu control register (liu_reg2) (402, a02) liu control register (liu_reg3) the default value of this register is e4 (hex) table 80. liu control register (liu_reg3) (403, a03). note: these registers must be written to 1 for the liu-to-framer interface to be functional. bit symbol description 0 reserved. write to 0. 1 reserved. write to 0. 2 losstd the losstd bit selects the conformance protocol for the dlos receiver alarm function. losstd = 0 selects standards t1m1.3/93-005, itu-t g.755 for ds1 mode and itu-t g.755 for cept mode. losstd = 1 selects standards tr-tsy- 000009 for ds1 and itu-t g.775 for cept. 3 reserved. write to 0. 4 highz the highz bit places the liu in a high-impedance state. when highz = 1, the ttip and tring transmit drivers for the specified channel are placed in a high- impedance state. 5 restart the restart bit is used for device initialization through the microprocessor inter- face. restart = 1 resets the data path circuits. data path circuits will be reset, but the microprocessor registers state will not be altered by a restart action. 67 reserved. write to 0. bit symbol description 0 jar the jar bit is used to enable and disable the jitter attenuator function in the receive path. the jar and jat control bits are mutually exclusive, i.e., either jar or the jat control bit can be set, but not both. jar = 1 places jitter attenuator in the receive path. 1 jat the jat bit is used to enable and disable the jitter attenuator function in the transmit path. the jat and jar control bits are mutually exclusive, i.e., either jat or the jar control bit can be set, but not both. jat = 1 places jitter attenuator in the transmit path. 2 code the code bit is used to enable and disable the b8zs/hdb3 zero substitution coding in the transmit and decoding in the receive path. code is used in conjunction with the dual bit and is valid only for single-rail operation. code = 1 activates the coding/ decoding functions. the default value is code = 1. 3 dual the dual bit is used to select single- or dual-rail mode of operation. dual = 1 selects the dual-rail mode. 4 lossd the lossd bit selects the shutdown function for the receiver during dlos. lossd operates in conjunction with the rcvais bit (see table 4, lossd and rcvais control configurations (not valid during loopback modes), repeated below for reference) 57 reserved. write to 1. preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 146 lucent technologies inc. lucent technologies inc. line interface control registers (continued) table 81. lossd and rcvais control configurations (not valid during loopback modes) (from table 4) liu control register (liu_reg4) table 82. liu register (liu_reg4) (404, a04) lossd rcvais alarm rpd/rnd rlck 0 0 alos 0 free runs 00dlos normal data recovered clock 1 0 alos 0 free runs 1 0 dlos 0 free runs 01alos ais (all ones) free runs 01dlos ais (all ones) free runs 1 1 alos 0 free runs 1 1 dlos 0 free runs bit symbol description 0 altimer the altimer bit is used to select the time required to declare alos. altimer = 0 selects 1 ms2.6 ms. altimer = 1 selects 10 bit to 255 bit periods. 1 rcvais the rcvais bit selects the shut down function for the receiver during alos alarm (alos). rcvais operates in conjunction with the lossd bit. see liu-reg3. 2 pflalm pflalm prevents the dlos alarm from occurring during flloop activation. pflalm = 1 activates the pflalm function. 3 prlalm prlalm prevents the lotc alarm from occurring during rloop activation/deacti- vation. prlalm = 1 activates the prlalm function. 4 phizalm phizalm prevents the tdm alarm from occurring when the driver are in a high- impedance state. phizalm = 1 activates the phizalm function. 5 jabw0 jabw0 = 1 selects the lower bandwidth jitter attenuator option in cept mode. lucent technologies inc. 147 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. line interface control registers (continued) liu configuration register (liu_reg5) the control bits in the channel configuration register 5 are used to select powerdown mode, ais generation, and loopbacks for the liu. the pwrdn and xlais bits are active-high. this is a read/write register. the default value of this register is 02 (hex). table 83. liu configuration register (liu_reg5) (405, a05) table 84. loopback control (from table 11) * the reset default condition is loopa = loopb = 0 (no loopback). ? during the transmit ais condition, the looped data will be the transmitted data from the framer or system interface and not t he all ones signal. ? transmit ais request is ignored. liu configuration register (liu_reg6) the control bits in the channel configuration register 6 are used to select liu transmit equalization settings. this is a read/write register. the default value of this register is 00 (hex) in ds1 when ds1/cept (pin 40/142) is set to 1, and 06 (hex) in cept when ds1/cept (pin 40/142) is set to 0. table 85. liu configuration register (liu_reg6) (406, a06) bit symbol description 0 pwrdn pwrdn = 1 activates powerdown. 1 xlais xlais = 1 enables transmission of an all ones signal to the line interface. xlais = 1 after a reset allowing immediate generation of alarm signal as long as a clock source is present. the default value is xlais = 1. 2 loopb the loopa bit is used in conjunction with loopb to select the channel loopback modes. see table 11, repeated below for reference. 3loopa 47 reserved. write to 0. operation symbol loopa loopb normal * 00 full local loopback flloop ? 01 remote loopback rloop ? 10 digital local loopback dlloop 1 1 bit symbol description 0 eq0 the eq0, eq1, and eq2 bits select the type of service (ds1 or cept) and the associated transmitter cable equalization/line build out/termination impedances. see table 7, transmit line interface short-haul equalizer/rate control, repeated below for reference. 1eq1 2eq2 37 reserved. write to 0. preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 148 lucent technologies inc. lucent technologies inc. line interface control registers (continued) table 86. transmit line interface short-haul equalizer/rate control (from table 7) * in ds1 mode, the distance to the dsx for 22-gauge pic (abam) cable is specified. use the maximum cable loss figures for other cable types. in cept mode, equalization is specified for coaxial or twisted-pair cable. ? reset default state is eq2, eq1, and eq0 = 000 when pin ds1_cept = 1 and eq2, eq1, and eq0 = 110 when pin ds1_cept = 0. ? loss measured at 772 khz. in 75 w applications, option 1 is recommended over option 2 for lower liu power dissipation. option 2 allows for the use of the same t rans- former as in cept 120 w applications (see line interface unit: line circuitry section). framer register architecture regbank3 and regbank6 contain the status and programmable control registers for the framer and system (chi) interface channels frm1 and frm2. the base address for regbank3 is 600 (hex) and for regbank6 is c00 (hex). within these register banks, the bit map is identical for both frm1 and frm2. the framer registers are structures as shown in table 87. default values are given in the individual register defini- tion tables. table 87. framer status and control blocks address range (hexadecimal) the complete register map for the framer is given in table 201 to table 203. all status registers are clocked with the internal framer receive line clock (rfrmck). bits in status registers frm_sr1 and frm_sr7 are set at the onset of the condition and are cleared on read when the given condition is no longer present. these registers can generate interrupts if the corresponding register bits are enabled in interrupt enable registers frm_pr0frm_pr7. short-haul applications eq2 eq1 eq0 service clock rate transmitter equalization *? maximum cable loss to dsx ? feet meters db 0 0 0 dsx-1 1.544 mhz 0 to 131 0 to 40 0.6 0 0 1 131 to 262 40 to 80 1.2 0 1 0 262 to 393 80 to 120 1.8 0 1 1 393 to 524 120 to 160 2.4 1 0 0 524 to 655 160 to 200 3.0 101cept 2.048 mhz 75 w (option 2) 1 1 0 120 w or 75 w (option 1) 111 not used framer register block status registers (cor) ((60063f); (c00c3f)) receive signaling registers ((64065f); (c40c5f)) parameter (configuration) registers ((6606a6); (c60ca6)) transmit signaling registers ((6e06ff); (ce0cff)) lucent technologies inc. 149 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. framer register architecture (continued) on all 16-bit counter registers (frm_sr8frm_sr51), both bytes are cleared only after reading both bytes. these status registers are two byte register pairs. these register pairs must be read in succession, with the lower byte read first followed by a read of higher byte. once a read is initiated on one of the bytes, the updating of that counter is disabled and remains disabled until both bytes are read. all events during this interval are lost. updating of the counter registers is stopped when all of the bits are set to 1. updating resumes after the registers are cleared on read. these register pairs may be read in any order, but they must be read in pairs, i.e., a read of 1 byte must be followed immediately by a read of the remaining byte of the pair. status registers frm_sr0frm_sr63 are clear-on-read (cor) registers. these registers are cleared by the framer internal received line clock (rfrmck). at least two rfrmck cycles (1.3 s for ds1 and 1.0 s for cept) must be allowed between successive reads of the same cor register to allow it to properly clear. framer status/counter registers registers frm_sr0frm_sr63 report the status of each framer. all are clear-on-read, read only registers. interrupt status register (frm_sr0) the interrupt pin (interrupt) goes active when a bit in this register and its associated interrupt enable bit in reg- isters frm_pr0frm_pr7 are set, and the interrupt for the framer block is enabled in register greg1. table 88. interrupt status register (frm_sr0) (600; c00) bit symbol description 0fac facility alarm condition. a 1 indicates a facility alarm occurred (go read frm_sr1). 1rac remote alarm condition. a 1 indicates a remote alarm occurred (go read frm_sr2). 2fae facility alarm event. a 1 indicates a facility alarm occurred (go read frm_sr3 and frm_sr4). 3ese errored second event. a 1 indicates an errored second event occurred (go read frm_sr5, frm_sr6, and frm_sr7). 4tssfe transmit signaling superframe event. a 1 indicates that a mos superframe block has been transmitted and the transmit signaling data buffers are ready for new data. 5rssfe receive signaling superframe event. a 1 indicates that a mos superframe block has been received and the receive signaling data buffers must be read. 6 reserved. 7 s96sr slc -96 stack ready. a 1 indicates that either the transmit framer slc -96 stack is ready for more data or the receive framer slc -96 stack contains new data. preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 150 lucent technologies inc. lucent technologies inc. framer register architecture (continued) facility alarm condition register (frm_sr1) the bits in the facility alarm condition register (frm_sr1) indicate alarm state of the receive framer section. inter- rupts from this register are generated once at the onset of the alarm condition. if the alarm condition is still present at the time of the read, the bit will remain in the 1 state for the duration of the alarm condition. if the alarm condition is no longer present at the time of the read, then the bit is cleared on read. table 89. facility alarm condition register (frm_sr1) (601; c01) bit symbol description 0lfa loss of frame alignment. a 1 indicates the receive framer is in a loss of frame align- ment and is currently searching for a new alignment. 1lsfa loss of signaling superframe alignment. a 1 indicates the receive framer is in a loss of signaling superframe alignment in the ds1 framing formats. a search for a new sig- naling superframe alignment starts once frame alignment is established. lts16mfa loss of time slot 16 signaling multiframe alignment. a 1 indicates the receive framer is in a loss of time slot 16 signaling multiframe alignment in the cept mode. a search for a new time slot 16 signaling multiframe alignment starts once frame alignment is established. this bit is 0 when the T7630 is programmed for the transparent signaling mode, register frm_pr44 bit 0 (tsig) = 1. 2ltsfa loss of transmit superframe alignment. a 1 indicates superframe alignment pattern in the transmit facility data link as defined for slc -96 is lost. only valid for slc -96 mode. this bit is 0 in all other ds1 modes. lts0mfa loss of time slot 0 crc-4 multiframe alignment. a 1 indicates an absence of crc- 4 multiframe alignment after initial basic frame alignment is established. a 0 indicates either crc-4 checking is disabled or crc-4 multiframe alignment has been success- fully detected. 3lfalr loss of frame alignment since last read. a 1 indicates that the lfa state indicated in bit 0 of this register is the same lfa state as the previous read. 4lbfa loss of biframe alignment. a 1 indicates that the cept biframe alignment pattern (alternating 10 in bit 2 of time slot 0 of each frame) in the receive system data is errored. this alignment pattern is required when transmitting the si or sa bits transparently. only valid in the cept mode. this bit is 0 in all other modes. 5rts16ais receive time slot 16 alarm indication signal. a 1 indicates the receive framer detected time slot 16 ais in the cept mode. this bit is 0 in the ds1 modes. 6auxp auxiliary pattern. a 1 indicates the detection of a valid auxp (unframed 1010 . . . pat- tern) in the cept mode. this bit is 0 in the ds1 modes. 7ais alarm indication signal. a 1 indicates the receive framer is currently receiving an ais pattern from its remote line end. lucent technologies inc. 151 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. framer register architecture (continued) remote end alarm register (frm_sr2) a bit set to 1 indicates the receive framer has recently received the given alarm. interrupts from this register are generated once at the beginning of the alarm condition. if the alarm is still present at the time of the read, the bit will remain in the 1 state for the duration of the alarm condition. if the alarm condition is no longer present at the time of the read, then the bit is cleared on read. table 90. remote end alarm register (frm_sr2) (602; c02) bit symbol description 0rfa remote framer alarm. a 1 indicates the receive framer detected a remote frame (yellow) alarm. 1rjya remote japanese yellow alarm. a 1 indicates the receive framer detected the japa- nese format remote frame alarm. rts16mfa remote multiframe alarm. a 1 indicates the receive framer detected a time slot 16 remote frame alarm in the cept mode. 2 crebit continuous received e bits. a 1 indicates the detection of a five-second interval containing 3 991 e bit = 0 events in each second. this bit is 0 in the ds1 mode. 3sa6 = 8 received sa6 = 8. a 1 indicates the receive framer detected a sa6 code equal to 1000. this bit is 0 in the ds1 mode. 4 sa6 = a received sa6 = a. a 1 indicates the receive framer detected a sa6 code equal to 1010. this bit is 0 in the ds1 mode. 5sa6 = c received sa6 = c. a 1 indicates the receive framer detected a sa6 code equal to 1100. this bit is 0 in the ds1 mode. 6 sa6 = e received sa6 = e. a 1 indicates the receive framer detected a sa6 code equal to 1110. this bit is 0 in the ds1 mode. 7sa6 = f received sa6 = f. a 1 indicates the receive framer detected a sa6 code equal to 1111. this bit is 0 in the ds1 mode. preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 152 lucent technologies inc. lucent technologies inc. framer register architecture (continued) facility errored event register (frm_sr3) a bit set to 1 indicates the receive framer has recently received the given errored event. table 91. facility errored event register-1 (frm_sr3) (603; c03) bit symbol description 0lfv line format violation. a 1 indicates the receive framer detected a bipolar line coding or excessive zeros violation. 1fbe frame-bit errored. a 1 indicates the receive framer detected a frame-bit or frame align- ment pattern error. 2 crce crc errored. a 1 indicates the receive framer detected crc errors. 3ece excessive crc errors. a 1 indicates the receive framer detected an excessive crc errored condition. this bit is only valid in the esf and cept with crc-4 modes; other- wise, it is 0. 4rebit received e bit = 0. a 1 indicates the receive framer detected a e bit = 0 in either frame 13 or 15 of the time slot 0 of crc-4 multiframe. this bit is 0 in the ds1 modes. 5 lcrcatmx lack of crc-4 multiframe alignment timer expire indication. a 1 indicates that either the 100 ms or the 400 ms crc-4 interworking timer expired. active only immedi- ately after establishment of the initial basic frame alignment. this bit is 0 in the ds1 modes. 6slipo receive elastic store slip: buffer overflow. a 1 indicates the receive elastic store per- formed a control slip due to an elastic buffer overflow condition. 7slipu receive elastic store slip: buffer underflow. a 1 indicates the receive elastic store performed a control slip due to an elastic buffer underflow condition. lucent technologies inc. 153 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. framer register architecture (continued) table 92. facility event register-2 (frm_sr4) (604; c04) bit symbol description 0nfa new frame alignment. a 1 indicates the receive framer established a new frame align- ment which differs from the previous alignment. 1ssfa signaling superframe alignment. a 1 indicates the receive framer has established the signaling superframe alignment. in the sf modes (d4 and slc -96) and cept modes, this alignment is established only after primary frame alignment is determined. 2llboff t1 line loopback off code detect. a 1 indicates the receive framer detected the ds1 line loopback disable code in the payload. this code is defined in at&t technical refer- ence 62411 as a framed 001 pattern where the frame bit is inserted into the pattern. bfa new biframe alignment established. a 1 indicates the transmit framer has established a biframe alignment for the transmission of transparent si and or sa bits from the system data in the cept mode. 3llbon t1 line loopback on code detect. a 1 indicates the receive framer detected the line loopback enable code in the payload. this code is defined in at&t technical reference 62411 as a framed 00001 pattern where the frame bit is inserted into the pattern. cma new cept crc-4 multiframe alignment. a 1 indicates the cept crc-4 multiframe alignment in the receive framer has been established. 4fdl-plbon esf fdl payload loopback on code detect. a 1 indicates the receive framer detected the line loopback enable code in the payload. this code is defined in ansi t1.403-1995 as a 1111111100101000 pattern in the facility data link, where the leftmost bit is the msb. slcrfsr slc -96 receive fdl stack ready. a 1 indicates that the receive fdl stack should be read. this bit is cleared on read. data in the receive fifo must be read within 9 ms of this interrupt. this bit is not updated during loss of frame or signaling superframe align- ment. 5fdl-plbof esf fdl payload loopback off code detect. a 1 indicates the receive framer detected the line loopback disable code in the payload. this code is defined in ansi t1.403-1995 as a 1111111101001100 pattern in the facility data link, where the leftmost bit is the msb. slctfsr slc -96 transmit fdl stack ready. a 1 indicates that the transmit fdl stack is ready for new data. this bit is cleared on read. data written within 9 ms of this interrupt will be transmitted in the next slc -96 d-bit superframe interval. 6fdl-llbon esf fdl line loopback on code detect. a 1 indicates the receive framer detected the line loopback enable code in the payload. this code is defined in ansi t1.403-1995 as a 1111111101110000 pattern in the facility data link, where the leftmost bit is the msb. rsasr cept receive sa stack ready. a 1 indicates that the receive sa6 stack should be read. this bit is clear on the first access to the sa receive stack or at the beginning of frame 0 of the crc-4 double-multiframe. data in the receive fifo must be read within 4 ms of this interrupt. this bit is not updated during lfa. 7 fdl-llboff esf fdl line loopback off code detect. a 1 indicates the receive framer detected the line loopback disable code in the payload. this code is defined in ansi t1.403-1995 as a 1111111100011100 pattern in the facility data link, where the leftmost bit is the msb. tsasr cept transmit sa stack ready. a 1 indicates that the transmit sa stack is ready for new data. this bit is cleared on the first access to the sa transmit stack or at the begin- ning of frame 0 of the crc-4 double multiframe. data written within 4 ms of this interrupt will be transmitted in the next crc-4 double multiframe interval. preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 154 lucent technologies inc. lucent technologies inc. framer register architecture (continued) the following registers are dedicated to the exchange termination and its remote end interface. the alarm condi- tions to trigger errored seconds and severely errored seconds are defined in table 44, event counters definition and the et and et-re enable registers, frm_pr14 and frm_pr15. the thresholds are defined in registers frm_pr11frm_pr13. table 93. exchange termination and exchange termination remote end interface status register (frm_sr5) (605; c05) bit symbol description 0etes et errored second. a 1 indicates the receive framer detected an errored second at the exchange termination (et). 1etbes et bursty errored second. a 1 indicates the receive framer detected a bursty errored second at the et. 2etses et severely errored second. a 1 indicates the receive framer detected a severely errored second at the et. 3etuas et unavailable state. a 1 indicates the receive framer has detected at least ten con- secutive severely errored seconds. upon detecting ten consecutive nonseverely errored seconds, the receive framer will clear this bit. itu recommendation g.826 is used resulting in a ten-second delay in the reporting of this condition. 4etrees et-re errored second. a 1 indicates the receive framer detected an errored second at the exchange termination remote end (et-re). 5 etrebes et-re bursty errored second. a 1 indicates the receive framer detected a bursty errored second at the et-re. 6 etreses et-re severely errored second. a 1 indicates the receive framer detected a severely errored second at the et-re. 7 etreuas et-re unavailable state. a 1 indicates the receive framer has detected at least ten consecutive severely errored seconds. upon detecting ten consecutive nonseverely errored seconds, the receive framer will clear this bit. itu recommendation g.826 is used resulting in a ten-second delay in the reporting of this condition. lucent technologies inc. 155 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. framer register architecture (continued) the following status registers are dedicated to the nt1 and the nt1 remote end (nt1-re) interface. the alarm conditions to evaluate errored seconds and severely errored seconds are defined in table 44, event counters def- inition and the nt1 and nt1-re enable registers, frm_pr16frm_pr18. the thresholds are defined in regis- ters frm_pr11frm_pr13. table 94. network termination and network termination remote end interface status register (frm_sr6) (606; c06) bit symbol description 0ntes nt errored second. a 1 indicates the receive framer detected an errored second at the network termination (nt). 1ntbes nt bursty errored second. a 1 indicates the receive framer detected a bursty errored second at the nt. 2ntses nt severely errored second. a 1 indicates the receive framer detected a severely errored second at the nt. 3ntuas nt unavailable state. a 1 indicates the receive framer has detected at least ten consec- utive severely errored seconds. upon detecting ten consecutive nonseverely errored sec- onds, the receive framer will clear this bit. itu recommendation g.826 is used resulting in a ten-second delay in the reporting of this condition. 4ntrees nt-re errored second. a 1 indicates the receive framer detected an errored second at the exchange termination remote end (et-re). 5 ntrebes nt-re bursty errored second. a 1 indicates the receive framer detected a bursty errored second at the et-re. 6 ntreses nt-re severely errored second. a 1 indicates the receive framer detected a severely errored second at the nt-re. 7ntreuas nt-re unavailable state. a 1 indicates the receive framer has detected at least ten consecutive severely errored seconds. upon detecting ten consecutive nonseverely errored seconds, the receive framer will clear this bit. itu recommendation g.826 is used resulting in a ten-second delay in the reporting of this condition. preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 156 lucent technologies inc. lucent technologies inc. framer register architecture (continued) bit 0bit 4 in this register are set high when the receive framer comes out of the unavailable state, while bit 4 bit 7 report detection of the receive test patterns. bits 4 and 5 are cleared only after register frm_pr70 bit 2 is set to 0. table 95. facility event register (frm_sr7) (607; c07) * it is possible for one of these bits to be set to 1, if the received line data is all zeros. bipolar violation counter register (frm_sr8frm_sr9) this register contains the 16-bit count of received bipolar violations, line code violations, or excessive zeros. table 96. bipolar violation counter registers (frm_sr8frm_sr9) ((608609); (c08c09)) frame bit errored counter register (frm_sr10frm_sr11) this register contains the 16-bit count of framing bit errors. framing bit errors are not counted during loss of frame alignment. table 97. framing bit error counter registers (frm_sr10frm_sr11) ((60a60b); (c0ac0b)) bit symbol description 0ouas out of unavailable state. a 1 indicates the receive framer detected ten consecutive sec- onds that were not severely errored while in the unavailable state at the et. 1erouas out of unavailable state at the et-re. a 1 indicates the receive framer detected ten con- secutive seconds that were not severely errored while in the unavailable state at the et-re. 2nt1ouas out of unavailable state at the nt1. a 1 indicates the receive framer detected ten consec- utive seconds that were not severely errored while in the unavailable state at the nt. 3nrouas out of unavailable state nt1-re. a 1 indicates the receive framer detected ten consecu- tive seconds that were not severely errored while in the unavailable state at the nt-re. 4detect test pattern detected. a 1 indicates the pattern detector has locked onto the pattern spec- ified by the ptrn configuration bits defined in register frm_pr70. 5 ptrnber test pattern bit error. a 1 indicates the pattern detector has found one or more single bit errors in the pattern that it is currently locked onto. 6rpsuedo receiving pseudorandom pattern. a 1 indicates the receive framer pattern monitor circuit is currently detecting the 2 15 C 1 pseudorandom pattern*. 7rquasi receiving quasi-random pattern. a 1 indicates the receive framer pattern monitor circuit is currently detecting the 2 20 C 1 quasi-random pattern*. register byte bit symbol description frm_sr8 msb 70 bpv15bpv8 bpvs counter. frm_sr9 lsb 70 bpv7bpv0 bpvs counter. register byte bit symbol description frm_sr10 msb 70 fbe15fbe8 frame bit errored counter. frm_sr11 lsb 70 fbe7fbe0 frame bit errored counter. lucent technologies inc. 157 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. framer register architecture (continued) crc error counter register (frm_sr12frm_sr13) this register contains the 16-bit count of crc errors. crc errors are not counted during loss of crc multiframe alignment. table 98. crc error counter registers (frm_sr12frm_sr13) ((60c60d); (c0cc0d)) e-bit counter register (frm_sr14frm_sr15) this register contains the 16-bit count of received e bit = 0 events. e bits are not counted during loss of cept crc-4 multiframe alignment. table 99. e-bit counter registers (frm_sr14frm_sr15) ((60e60f); (c0ec0f)) crc-4 errors at nt1 from nt2 counter registers (frm_sr16frm_sr17) this register contains the 16-bit count of each occurrence of sa6 code 001x, detected synchronously to the cept crc-4 multiframe. table 100. crc-4 errors at nt1 from nt2 counter registers (frm_sr16frm_sr17) ((610611); (c10c11)) e bit at nt1 from nt2 counter registers (frm_sr18frm_sr19) this register contains the 16-bit count of each occurrence of sa6 code 00x1, detected synchronously to the cept crc-4 multiframe. e bits are not counted during loss of cept crc-4 multiframe alignment. table 101. e bit at nt1 from nt2 counter (frm_sr18frm_sr19) ((612613); (c12c13)) register byte bit symbol description frm_sr12 msb 70 cec15cec8 crc errored counter. frm_sr13 lsb 70 cec7cec0 crc errored counter. register byte bit symbol description frm_sr14 msb 70 rec15rec8 e-bit counter. frm_sr15 lsb 70 rec7rec0 e-bit counter. register byte bit symbol description frm_sr16 msb 70 cnt15cnt8 crc-4 errors at nt1 counter. frm_sr17 lsb 70 cnt7cnt0 crc-4 errors at nt1 counter. register byte bit symbol description frm_sr18 msb 70 ent15ent8 e bit at nt1 counter. frm_sr19 lsb 70 ent7ent0 e bit at nt1 counter. preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 158 lucent technologies inc. lucent technologies inc. framer register architecture (continued) the following status registers, frm_sr20frm_sr51, contain the 16-bit count of errored seconds, bursty errored seconds, severely errored seconds, and unavailable seconds at the et, et-re, nt1, and nt1-re termi- nals. ds1 error conditions are reported in the et errored registers frm _sr20frm_sr35. table 102. et errored seconds counter (frm_sr20frm_sr21) ((614615); (c14c15)) table 103. et bursty errored seconds counter (frm_sr22frm_sr23) ((616617); (c16c17)) table 104. et severely errored seconds counter (frm_sr24frm_sr25) ((618619); (c18c19)) table 105. et unavailable seconds counter (frm_sr26frm_sr27) ((61a61b); (c1ac1b)) table 106. et-re errored seconds counter (frm_sr28frm_sr29) ((61c61d); (c1cc1d)) table 107. et-re bursty errored seconds counter (frm_sr30frm_sr31) ((61e61f); (c1ec1f)) table 108. et-re severely errored seconds counter (frm_sr32frm_sr33) ((620621); (c20c21)) register byte bit symbol description frm_sr20 msb 70 etes15etes8 et errored seconds counter. frm_sr21 lsb 70 etes7etes0 et errored seconds counter. register byte bit symbol description frm_sr22 msb 70 etbes15etbes8 et bursty errored seconds counter. frm_sr23 lsb 70 etbes7etbes0 et bursty errored seconds counter. register byte bit symbol description frm_sr24 msb 70 etses15etses8 et severely errored seconds counter. frm_sr25 lsb 70 etses7etses0 et severely errored seconds counter. register byte bit symbol description frm_sr26 msb 70 etus15etus8 et unavailable seconds counter bits. frm_sr27 lsb 70 etus7etus0 et unavailable seconds counter bits. register byte bit symbol description frm_sr28 msb 70 etrees15etrees8 et-re errored seconds counter. frm_sr29 lsb 70 etrees7etrees0 et-re errored seconds counter. register byte bit symbol description frm_sr30 msb 70 etrebes15etrebes8 et-re bursty errored seconds counter. frm_sr31 lsb 70 etrebes7etrebes0 et-re bursty errored seconds counter. register byte bit symbol description frm_sr32 msb 70 etreses15etreses8 et-re severely errored seconds counter. frm_sr33 lsb 70 etreses7etreses0 et-re severely errored seconds counter. lucent technologies inc. 159 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. framer register architecture (continued) table 109. et-re unavailable seconds counter (frm_sr34frm_sr35) ((622623); (c22c23)) table 110. nt1 errored seconds counter (frm_sr36frm_sr37) ((624625); (c24c25)) table 111. nt1 bursty errored seconds counter (frm_sr38frm_sr39) ((626627); (c26c27)) table 112. nt1 severely errored seconds counter (frm_sr40frm_sr41) ((628629); (c28c29)) table 113. nt1 unavailable seconds counter (frm_sr42frm_sr43) ((62a62b); (c2ac2b)) table 114. nt1-re errored seconds counter (frm_sr44frm_sr45) ((62c62d); (c2cc2d)) table 115. nt1-re bursty errored seconds counter (frm_sr46frm_sr47) ((62e62f); (c2ec2f)) register byte bit symbol description frm_sr34 msb 70 etreus15etreses8 et-re unavailable seconds counter. frm_sr35 lsb 70 etreses7etreses0 et-re unavailable seconds counter. register byte bit symbol description frm_sr36 msb 70 ntes15ntes8 nt1 errored seconds counter. frm_sr37 lsb 70 ntes7ntes0 nt1 errored seconds counter. register byte bit symbol description frm_sr38 msb 70 ntbes15ntbes8 nt1 bursty errored seconds counter. frm_sr39 lsb 70 ntbes7ntbes0 nt1 bursty errored seconds counter. register byte bit symbol description frm_sr40 msb 70 ntses15ntses8 nt1 severely errored seconds counter. frm_sr41 lsb 70 ntses7ntses0 nt1 severely errored seconds counter. register byte bit symbol description frm_sr42 msb 70 ntus15ntus8 nt1 unavailable seconds counter bits. frm_sr43 lsb 70 ntus7ntus0 nt1 unavailable seconds counter bits. register byte bit symbol description frm_sr44 msb 70 ntrees15ntrees8 nt1-re errored seconds counter. frm_sr45 lsb 70 ntrees7ntrees0 nt1-re errored seconds counter. register byte bit symbol description frm_sr46 msb 70 ntrebes15ntrebes8 nt1-re bursty errored seconds counter. frm_sr47 lsb 70 ntrebes7ntrebes0 nt1-re bursty errored seconds counter. preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 160 lucent technologies inc. lucent technologies inc. framer register architecture (continued) table 116. nt1-re severely errored seconds counter (frm_sr48frm_sr49) ((630631); (c30c31)) table 117. nt1-re unavailable seconds counter (frm_sr50frm_sr51) ((632633); (c32c33)) received not-fas ts0 rsa register (frm_sr52) this register contains the last (since last read) valid received rsa8rsa4 bits, a bit, and si bit of not-fas time slot 0 and the si bit of fas time slot 0 while the receive framer was in basic frame alignment. table 118. receive not-fas ts0 register (frm_sr52) (634; c34) received sa register (frm_sr53) this register contains the last (since last read) valid time slot 16 spare bits of the frame containing the time slot 16 signaling multiframe alignment. these bits are updated only when the receive framer is in signaling multiframe alignment. table 119. receive sa register (frm_sr53) (635; c35) register byte bit symbol description frm_sr48 msb 70 ntreses15ntreses8 nt1-re severely errored seconds counter. frm_sr49 lsb 70 ntreses7ntreses0 nt1-re severely errored seconds counter. register byte bit symbol description frm_sr50 msb 70 ntreus15ntreus8 nt1-re unavailable seconds counter bits. frm_sr51 lsb 70 ntreus7ntreus0 nt1-re unavailable seconds counter bits. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 not-fas bit 1 (cept without crc-4) or frame 15 e bit (cept with crc-4) fas bit 1 (cept without crc-4) or frame 13 e bit (cept with crc-4) a bit sa4 sa5 sa6 sa7 sa8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00000x2x1x0 lucent technologies inc. 161 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. framer register architecture (continued) slc- 96 fdl/cept sa receive stack (frm_sr54frm_sr63) in the slc -96 frame format, frm_sr54 through frm_sr58 contain the received slc -96 facility data link data block. when the framer is in a loss of frame alignment or loss of signaling superframe alignment, these registers are not updated. note: the rsp[1:4] are the received spoiler bits. table 12 0 . slc- 96 fdl receive stack (frm_sr54frm_sr63) ((63663f); (c36c3f)) in the cept frame format, frm_sr54 through frm_sr63 contain the received sa4 through sa8 from the last valid crc-4 double-multiframe. in non-crc-4 mode, these registers are only updated during a basic frame-aligned state. in crc-4 mode, these registers are only updated during the crc-4 multiframe alignment state. table 121. cept sa receive stack (frm_sr54frm_sr63) ((63663f); (c36c3f)) register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 frm_sr54 0 0 r-0 r-0 r-0 r-1 r-1 r-1 frm_sr55 0 0 r-0 r-0 r-0 r-1 r-1 r-1 frm_sr56 rc 1 rc 2 rc 3 rc 4 rc 5 rc 6 rc 7 rc 8 frm_sr57 rc 9 rc 10 rc 11 rspb 1 = 0 rspb 2 = 1 rspb 3 = 0 rm 1 rm 2 frm_sr58 rm 3 ra 1 ra 2 rs 1 rs 2 rs 3 rs 4 rspb 4 = 1 frm_sr59 frm_sr61 000 0 0 0 0 0 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 frm_sr54 sa4-1 sa4-3 sa4-5 sa4-7 sa4-9 sa4-11 sa4-13 sa4-15 frm_sr55 sa4-17 sa4-19 sa4-21 sa4-23 sa4-25 sa4-27 sa4-29 sa4-31 frm_sr56 sa5-1 sa5-3 sa5-5 sa5-7 sa5-9 sa5-11 sa5-13 sa5-15 frm_sr57 sa5-17 sa5-19 sa5-21 sa5-23 sa5-25 sa5-27 sa5-29 sa5-31 frm_sr58 sa6-1 sa6-3 sa6-5 sa6-7 sa6-9 sa6-11 sa6-13 sa6-15 frm_sr59 sa6-17 sa6-19 sa6-21 sa6-23 sa6-25 sa6-27 sa6-29 sa6-31 frm_sr60 sa7-1 sa7-3 sa7-5 sa7-7 sa7-9 sa7-11 sa7-13 sa7-15 frm_sr61 sa7-17 sa7-19 sa7-21 sa7-23 sa7-25 sa7-27 sa7-29 sa7-31 frm_sr62 sa8-1 sa8-3 sa8-5 sa8-7 sa8-9 sa8-11 sa8-13 sa8-15 frm_sr63 sa8-17 sa8-19 sa8-21 sa8-23 sa8-25 sa8-27 sa8-29 sa8-31 preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 162 lucent technologies inc. lucent technologies inc. framer register architecture (continued) the receive framer stores the current second of the ansi performance report message transmitted to the remote end in registers frm_sr62 and frm_sr63. the structure of the prm status registers is shown in table 122. table 122. transmit framer ansi performance report message status register structure received signaling registers: ds1 format table 123. received signaling registers: ds1 format (frm_rsr0frm_rsr23) ((640658); (c40c58)) 1. bit 6 and bit 5 of the ds1 receive signaling registers are copied from bit 6 and bit 5 of the ds1 transmit signaling registe rs. receive signaling registers: cept format table 124. receive signaling registers: cept format (frm_rsr0frm_rsr31) ((64065f); (c40c5f)) 1. in pcs0 or pcs1 signaling mode, this bit is undefined. transmit framer prm status bytes tsprm b7 tsprm b6 tsprm b5 tsprm b4 tsprm b3 tsprm b2 tsprm b1 tsprm b0 frm_sr62 g3 lv g4 u1 u2 g5 sl g6 frm_sr63 fe se lb g1 r g2 nm nl received signal registers bit 7 bit 6 1 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ds1 received signaling registers (023) p g f x d c b a voice channel with 16-state signaling x 0 0 x d c b a voice channel with 4-state signaling x 0 1 x x x b a voice channel with 2-state signaling x 1 1 x x x x a data channel x 1 0 x x x x x receive signal registers bit 7 bit 65 bit 4 1 bit 3 bit 2 bit 1 bit 0 frm_rsr1frm_rsr15 p x e[1:15] d[1:15] c[1:15] b[1:15] a[1:15] frm_rsr[17:31] p x e[17:31] d[17:31] c[17:31] b[17:31] a[17:31] lucent technologies inc. 163 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. framer register architecture (continued) registers frm_pr0frm_pr70 define the mode configuration of each framer. all are read/write registers. these registers are initially set to a default value upon a hardware reset, which is indicated in the register definition. interrupt group enable registers (frm_pr0frm_pr7) the bits in this register group enable the status registers frm_sr0frm_sr7 to assert the interrupt pin. the default value of these registers is 00 (hex). frm_pr0 is the primary interrupt group enable register which enables the event groups in interrupt status register frm_sr0. a bit set to 1 in this register enables the corresponding bit in the interrupt status register frm_sr0 to assert the interrupt pin. frm_pr1frm_pr7 are the secondary interrupt enable registers. a bit set to 1 in these registers enables the corresponding bit in the status register to assert the interrupt pin. table 125. summary of interrupt group enable registers (frm_pr0frm_pr7) ((660667); (c60c67)) parameter /control register status register enabled status register bit 7 status register bit 6 status register bit 5 status register bit 4 status register bit 3 status register bit 2 status register bit 1 status register bit 0 frm_pr0 frm_sr0 s96sr reserved rssfe tssfe ese (read frm_sr5, frm_sr6, and frm_sr7) fa e (read frm_sr3 and frm_sr4) rac (read frm_sr2) fac (read frm_sr1) frm_pr1 frm_sr1 ais auxp rts16ais lbfa lfalr ltsfa (lts0mfa) lsfa (lts16mfa) lfa frm_pr2 frm_sr2 rsa6 = f rsa6 = e rsa6 = c rsa6 = a rsa6 = 8 crebit rjya (rts16mfa) rfa frm_pr3 frm_sr3 slipu slipo lcrcatmx rebit ece crce fbe lfv frm_pr4 frm_sr4 fdl_llboff (tsasr) fdl_llbon (rsasr) fdl_plboff (slctfsr) fdl_plbon (slcrfsr) llbon (cma) llboff (bfa) ssfa cfa frm_pr5 frm_sr5 etreuas etreses etrebes etrees etuas etses etbes etes frm_pr6 frm_sr6 ntreuas ntreses ntrebes ntrees ntuas ntses ntbes ntes frm_pr7 frm_sr7 rquasi rpsuedo ptrnber detect nrouas nt1ouas erouas ouas preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 164 lucent technologies inc. lucent technologies inc. framer register architecture (continued) primary interrupt enable register (frm_pr0) the default value of this register is 00 (hex). table 126. primary interrupt group enable register (frm_pr0) (660; c60) bit symbol description 0sr1ie status register 1 interrupt enable bit. a 1 enables register frm_sr1 event interrupts. 1sr2ie status register 2 interrupt enable bit. a 1 enables register frm_sr2 event interrupts. 2sr34ie status registers 3 and 4 interrupt enable bit. a 1 enables registers frm_sr3 and frm_sr4 event interrupts. 3sr567ie status registers 5, 6, and 7 interrupt enable bit. a 1 enables registers frm_sr5, frm_sr6, and frm_sr7 event interrupts. 4tsrie transmit signaling ready interrupt enable bit. a 1 enables interrupts when transmit signaling buffers are ready (mos mode). 5rsrie receive signaling ready interrupt enable bit. a 1 enables interrupts when receive sig- naling buffers are ready (mos mode). 6 reserved . write to 0. 7slcie slc -96 interrupt enable bit. a 1 enables interrupts when slc -96 receive or transmit stacks are ready. lucent technologies inc. 165 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. framer register architecture (continued) secondary interrupt enable registers (frm_pr1frm_pr7) a bit set to 1 in registers frm_pr1frm_pr7 enables the generation of interrupts whenever the corresponding bit in registers frm_sr1frm_sr7 is set. the default value of these registers is 00 (hex). table 127. interrupt enable register (frm_pr1) (661; c61) table 128. interrupt enable register (frm_pr2) (662; c62) table 129. interrupt enable register (frm_pr3) (663; c63) table 130. interrupt enable register (frm_pr4) (664; c64) table 131. interrupt enable register (frm_pr5) (665; c65) table 132. interrupt enable register (frm_pr6) (666; c66) table 133. interrupt enable register (frm_pr7) (667; c67) bit symbol description 07 sr1b0ie sr1b7ie status register 1 interrupt enable. a 1 enables events monitored in register frm_sr1 to generate interrupts. each bit position in this enable register corresponds to the same bit position in the status register. bit symbol description 07 sr2b0ie sr2b7ie status register 2 interrupt enable. a 1 enables events monitored in register frm_sr2 to generate interrupts. each bit position in this enable register corresponds to the same bit position in the status register. bit symbol description 07 sr3b0ie sr3b7ie status register 3 interrupt enable. a 1 enables events monitored in register frm_sr3 to generate interrupts. each bit position in this enable register corresponds to the same bit position in the status register. bit symbol description 07 sr4b0ie sr4b7ie status register 4 interrupt enable. a 1 enables events monitored in register frm_sr4 to generate interrupts. each bit position in this enable register corresponds to the same bit position in the status register. bit symbol description 07 sr5b0ie sr5b7ie status register 5 interrupt enable. a 1 enables events monitored in register frm_sr5 to generate interrupts. each bit position in this enable register corresponds to the same bit position in the status register. bit symbol description 07 sr6b0ie sr6b7ie status register 6 interrupt enable. a 1 enables events monitored in register frm_sr6 to generate interrupts. each bit position in this enable register corresponds to the same bit position in the status register. bit symbol description 07 sr7b0ie sr7b7ie status register 7 interrupt enable. a 1 enables events monitored in register frm_sr7 to generate interrupts. each bit position in this enable register corresponds to the same bit position in the status register. preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 166 lucent technologies inc. lucent technologies inc. framer register architecture (continued) framer mode option register (frm_pr8) the default value of this register is c0 (hex). table 134. framer mode bits decoding (frm_pr8) (668; c68) table 135. line code option bits decoding (frm_pr8) (668; c68) frm_pr8 frame format bit 7 bit 6 bit 5 bit 4 fmode4 bit 3 fmode3 bit 2 fmode2 bit 1 fmode1 bit 0 fmode0 esf xxx00000 d4 xxx00001 dds xxx00010 dds with fdl xxx00011 slc -96 xxx00100 transmit esf receive d4xxx10000 transmit d4 receive esfxxx10001 cept with no crc-4 pcs mode 0xxx01001 pcs mode 1xxx01010 cept with crc-4 pcs mode 0xxx01101 pcs mode 1xxx01110 line code format bit 7 lc2 bit 6 lc1 bit 5 lc0 bit 4 bit 3 bit 2 bit 1 bit 0 b8zs (t/r) 0 0 0 xxxxx zcs (t/r) 0 0 1 xxxxx hdb3 (t/r) 0 1 0 xxxxx single rail (default) 1 1 0 xxxxx ami (t/r) 0 1 1 xxxxx b8zs (t), ami (r) 1 0 0 xxxxx zcs (t), b8zs (r) 1 0 1 xxxxx ami (t), b8zs (r) 1 1 1 xxxxx lucent technologies inc. 167 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. framer register architecture (continued) framer crc control option register (frm_pr9) this register defines the crc options for the framer. the default setting is 00 (hex). table 136. crc option bits decoding (frm_pr9) (669, c69) alarm filter register (frm_pr10) the bits in this register enable various control options. the default setting is 00 (hex). table 137. alarm filter register (frm_pr10) (66a; c6a) frm_pr9 crc options bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 loss of frame alignment due to excessive crc errors (esf 3 320, cept 3 915 in a one-second interval) 0xxxxx11 crc-4 with 100 ms timer 0 x x x x 1 x 1 crc-4 interworking search with 400 ms timer 0 x x x 1 x x 1 crc-4 with 990 reb counter 0 x x 1 x x x 1 crc-4 with 990 reb counter: a bit = 1 restart 0 x 1 1 x x x 1 crc-4 with 990 reb counter: sa6-f or sa6-e restart 0 1x1xxx1 xcrc-4/r-no crc-4 1 x x x x x x 0 x-nocrc-4/rcrc4 1 x x x x x x 1 crc default mode (no crc) 0 0 000000 bit symbol description 0 ssa6m synchronous sa6 monitoring. a 0 enables the asynchronous monitoring of the sa6 codes relative to the receive crc-4 submultiframe. a 1 enables synchronous monitoring of the sa6 pattern relative to the receive crc-4 submultiframe. 1aism ais detection mode. a 0 enables the detection of received line ais as described in etsi draft prets 300 233:1992. a 1 enables the detection of received line ais as described in itu rec. g.775. 2 feren fer enable. a 0 enables only the detection of f t framing bit errors in d4 and slc -96 modes. a 1 enables the detection of f t and f s framing bit errors. 3 cnuclben cnuclb enable. a 0 enables payload loopback with regenerated/crc bits in register frm_pr24. a 1 enables cept nailed-up connect loopback in register frm_pr24. 45 reserved. set to 0. preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 168 lucent technologies inc. lucent technologies inc. framer register architecture (continued) bit 6 and bit 7 of frm_pr10 control the evaluation of the bursty errored parameter as defined in table 138 below. the est parameter refers to the errored second threshold defined in register frm_pr11. the sest parameter refers to the severely errored second threshold defined in registers frm_pr12 and frm_pr13. table 138. errored event threshold definition errored second threshold register (frm_pr11) this register defines the errored event threshold for an errored second (es). a one-second interval with errors less than the es threshold value will not be detected as an errored second. programming 00 (hex) into this register dis- ables the errored second threshold monitor circuitry if register frm_pr10 bit 6 = 1 and bit 7 = 0. the default value of this register is 00 (hex). table 139. errored second threshold register (frm_pr11) (66b; c6b) severely errored second threshold register (frm_pr12frm_pr13) this 16-bit register defines the errored event threshold for a severely errored second (ses). a one-second interval with errors less than the ses threshold value is not a severely errored second. programming 00 (hex) into these two registers disables the severely errored second threshold monitor circuitry if register frm_pr10 bit 6 = 1 and bit 7 = 0. the default value of these registers is 00 (hex). table 140. severely errored second threshold registers (frm_pr12frm_pr13) ((66c66d; c6cc6d)) bit 7, frm_pr10 esm1 bit 6, frm_pr10 esm0 errored second (es) definition bursty errored second (bes) definition severely errored second (ses) definition 0 0 default values in table 44. event counters definition. 0 1 es = 1 when: errored events > est bes = 0 ses = 1 when: errored events > sest other combinations reserved. register symbol description frm_pr11 est7est0 es threshold register. register symbol description frm_pr12 sest15sest8 ses msb threshold register. frm_pr13 sest7sest0 ses lsb threshold register. lucent technologies inc. 169 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. framer register architecture (continued) et1 errored event enable register * (frm_pr14) these bits enable the errored events used to determine errored and severely errored seconds at the local et inter- face. etslip, etais, etlmfa, and etlfa are the slip, ais, lmfa, and lfa errored events, respectively, as referred to the local et interface. a 1 in the bit position enables the corresponding errored event. the default value of this register is 00 (hex). table 141. et1 errored event enable register (frm_pr14) (66e; c6e) et1 remote end errored event enable register * (frm_pr15) these bits enable the errored events used to determine errored and severely errored seconds at the et's remote end interface. etresa6-f, etresa6-e, etresa6-8, etrerfa, etreslip, etreais, etrelmfa, and etrelfa are the sa6-f, sa6-e, sa6-8, rfa, slip, ais, lmfa, and lfa errored events, respectively, as referred to the et remote end interface. a 1 in the bit position enables the corresponding errored event. the default value of this register is 00 (hex). table 142. et1 remote end errored event enable register (frm_pr15) (66f; c6f) nt1 errored event enable register * (frm_pr16) these bits enable the errored events used to determine errored and severely errored seconds at the network termi- nation-1 interface. ntsa6-c, ntsa6-8, ntslip, ntais, ntlmfa, and ntlfa are the sa6-c, sa6-8, slip, ais, lmfa, and lfa errored events, respectively, as referred to the nt1 interface. a 1 in the bit position enables the cor- responding errored event. the default value of this register is 00 (hex). table 143. nt1 errored event enable register (frm_pr16) (670; c70) nt1 remote end errored event enable register * (frm_pr17frm_pr18) these bits enable the errored events used to determine errored and severely errored seconds at the network termi- nation-1 remote end interface. ntrerfa, ntreslip, ntreais, ntrelmfa, ntrelfa, ntresa6-c, ntresa6-f, ntresa6-e, and ntresa6-8 are the rfa, slip, ais, lmfa, lfa, sa6-c, sa6-f, sa6-e, and sa6-8 errored events, respectively, as referred to the nt-1 remote end interface. the default value of this register is 00 (hex). table 144. nt1 remote end errored event enable registers (frm_pr17frm_pr18) ((671672); (c71c72)) * one occurrence of any one of these events causes an errored second count increment and a severely errored second count increm ent. register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 frm_pr14 0 0 0 0 etslip etais etlmfa etlfa register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 frm_pr15 etresa6-f etresa6-e etresa6-8 etrerfa etreslip etreais etrelmfa etrelfa register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 frm_pr16 ntsa6-c 0 ntsa6-8 0 ntslip ntais ntlmfa ntlfa register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 frm_pr17 0 0 0 ntrerfa ntreslip ntreais ntrelmfa ntrelfa frm_pr18 0 0 0 0 ntresa6-c ntresa6-f ntresa6-e ntresa6-8 preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 170 lucent technologies inc. lucent technologies inc. framer register architecture (continued) automatic ais to the system and automatic loopback enable register the default value of this register is 00 (hex). table 145. automatic ais to the system and automatic loopback enable register (frm_pr19) (673; c73) transmit test pattern to the line enable register * this register enables the transmit framer to transmit various test signals to the line interface. the default value of this register is 00 (hex). note that between enabling the transmission of line loopback on and off codes this register must be set to 00 (hex) (i.e., to enable transmission of line loopback on code and then off code, write into this reg- ister 10 (hex), then 00 (hex), and finally 20 (hex)). table 146. transmit test pattern to the line enable register (frm_pr20) (674; c74 ) * to transmit test signals using this register, registers frm_pr69 and frm_pr70 must be set to 00 (hex). bit symbol description 0 asais automatic system ais. a 1 transmits ais to the system whenever the receive framer is in the loss of receive frame alignment (rlfa) state. 1asaistmx automatic system ais cept crc-4 timer expiration. a 1 transmits ais to the sys- tem after the crc-4 100 ms or 400 ms timer expires. ais is transmitted for the duration of the loss of crc-4 multiframe alignment state. 2 reserved. set to 0. 3tsais transmit system ais. a 1 transmits ais to the system. 4allbe automatic line loopback enable. a 1 enables the framer section to execute the ds1 line loopback on or off commands without system intervention. 5 reserved. set to 0. 6 afdllbe automatic fdl line loopback enable. a 1 enables the framer section to execute a line esf fdl loopback on or off command without system intervention. 7 afdplbe automatic fdl payload loopback enable. a 1 enables the framer section to execute a payload esf fdl loopback on or off command without system intervention. bit symbol description 0tufais unframed ais to line interface (all ones pattern). 1tufauxp unframed auxp to line interface in cept mode (alternating 010101 unframed pattern). 2tprs transmit pseudorandom signal to line interface (2 15 C 1). 3tqrs transmit quasi-random signal to line interface (2 20 C 1) ( ansi t1.403). 4tllbon transmit framed payload line loopback on code: 00001. 5tllboff transmit framed payload line loopback off code: 001. 6tlic transmit line idle code of frm_pr22. when this bit = 1, the line idle code of frm_pr22 is transmitted to the line in all time slots. 7 ticrc transmit inverted crc. lucent technologies inc. 171 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. framer register architecture (continued) framer fdl control command register (frm_pr21) the default value of this register is 00 (hex). table 147. framer fdl control command register (frm_pr21) (675; c75) framer transmit line idle code register (frm_pr22) the value programmed in this register is transmitted as the line idle code. the default value is 7f (hex). table 148. framer transmit line idle code register (frm_pr22) (676; c76) framer system stuffed time-slot code register (frm_pr23) the value programmed in this register is transmitted in the stuffed time slots on the chi in the ds1 modes. the default value is 7f (hex). table 149. framer system stuffed time-slot code register (frm_pr23) (677; c77) bit symbol description 0 reserved. must be set to 0. 1 reserved. must be set to 0. 2 reserved. must be set to 0. 3 reserved. must be set to 0. 4 tfdllais transmit facility data link ais to the line. a 1 sends ais in the line side data link. 5 tfdlsais transmit facility data link ais to the system. a 1 sends ais in the system data link side. 6 tfdlc transmit fdl control bit. a 0 enables the transmission of the fdl bit from the internal fdl-hdlc unit (default). a 1 enables the transmission of the fdl bit from either tfdl input (pin 67 and 115) or from the internal transmit stack depending on the state of frm_pr29 bit 5bit 7. when the slc -96 stack transmission is enabled (register frm_pr26 bit 5bit 7 = x10 (binary), the fdl bit is sourced from the slc -96 transmit stack (register frm_pr31frm_pr35). otherwise, it is sourced from tfdl (pins 67/115). 7 tc/r = 1 transmit esf_prm c/r = 1 (tc/r = 1). a 0 transmits the esf performance report mes- sage with the c/r bit = 0. (see ansi t1.403-1995 for the prm structure and content.) a 1 transmits the esf performance report message with the c/r bit = 1. bit symbol description 07 tlic0tlic7 transmit line idle code 07. these 8 bits define the idle code transmitted to the line. bit symbol description 07 sstsc0 sstsc7 system stuffed time-slot code 07. these 8 bits define the idle code transmitted in the stuffed time slots to the system (chi). preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 172 lucent technologies inc. lucent technologies inc. framer register architecture (continued) primary loopback mode control and time-slot address (frm_pr24) this register contains the loopback mode control and the 5-bit address of the line or system time slot to be looped back. the default value is 00 (hex) (no loopback). table 150. primary time-slot loopback address register (frm_pr24) (678; c78) table 151. loopback decoding of bits lbc[2:0] in frm_pr24, bits 75 bit symbol description 04 tslba0 tslba4 time-slot loopback address. 57 lbc0lbc2 loopback control bits[2:0]. lbc2 lbc1 lbc0 function 000 no loopback. 001 line loopback (llb). the received line data is looped back to the transmit line data. 010 board loopback (blb). the received system data is looped back to the transmit system data, and ais is sent as the line transmit data. 011 single time-slot system loopback (stsslb). system (chi) loopback of the time slot selected by bit 4bit 0. idle code selected by frm_pr22 is inserted in the line payload in place of the looped back time slot. 100 single time-slot line loopback (stsslb). line loopback of time slot selected by bit 4bit 0. idle code selected by frm_pr22 is inserted in the system (chi) payload in place of the looped back time slot. 101 cept nailed-up broadcast transmission (cnubt). time slot selected by bit 4 bit 0 is transmitted normally and also placed into time slot 0. 110 payload line loopback with regenerated framing and crc bits. this mode is selected if frm_pr10 bit 3 = 0. the received channelized-payload data is looped backed to the line. the framing bits are generated within the transmit framer. the regenerated framing information includes the f-bit pattern, the crc checksum bit, and the systems facility data link bit stream. this loopback mode can be used with the cept framing mode. the entire time slot 0 data (fas and not fas) is regenerated by the transmit framer. the receive framer processes and monitors the incoming line data normally in this loopback mode and transmits the formatted data to the system in the normal format via the chi. cept nailed-up connect loopback (cnuclb). the received system time slot selected by this register bit 4bit 0 is looped back to the system in time slot 0. this mode is selected if frm_pr10 bit 3 = 1. 111 payload line loopback with passthrough framing and crc bits. the received channelized/payload data, the crc bits, and the frame alignment bits are looped back to the line. the systems facility data link bit stream is inserted into the looped back data and transmitted to the line. in esf, the fdl bits are ignored when calculating the crc-6 checksum. in cept, the fdl bits are included when calculating the crc-4 checksum, and as such, this loopback mode generates crc-4 errors back at the remote end. lucent technologies inc. 173 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. framer register architecture (continued) secondary loopback control and id and address (frm_pr25) this register allows for a second single-time-slot loopback mode. this loopback is valid if the secondary time-slot loopback address is different from the primary loopback address and the device is not in a line, board, or payload loopback, see frm_pr24. this register contains the secondary loopback mode control and the 5-bit address for the secondary line or system time slot to be looped back to the line or system. the default value is 00 (hex) (no loopback). table 152. secondary time-slot loopback address register (frm_pr25) (679; c79) table 153. loopback decoding of bits lbc[1:0] in frm_pr25, bits 65 bit symbol description 04 stslba0stslba4 secondary time-slot loopback address. 56 slbc0slbc1 secondary loopback control bits[1:0]. 7 reserved. write to 0. lbc1 lbc0 function 00 no loopback. 01 secondary single time-slot system loopback. 10 secondary single time-slot line loopback. 11 reserved. preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 174 lucent technologies inc. lucent technologies inc. framer register architecture (continued) framer reset and transparent mode control register (frm_pr26) the default value of this register is 00 (hex). table 154. framer reset and transparent mode control register (frm_pr26) (67a, c7a) bits symbol description 0 swreset framer software reset. the framer and fdl sections are placed in the reset state for four clock cycles of the frame internal line clock (rfrmck). the parameter registers are forced to the default values. this bit is self-cleared. 1 swrestart framer software restart. the framer and fdl sections are placed in the reset state as long as this bit is set to 1. the framers parameter registers are not changed from their programmed state. the fdl parameter registers are changed from their programmed state. this bit must be cleared. 2 frfrm framer reframe. a 0-to-1 transition of this bit forces the receive framer into the loss of frame alignment (lfa) state which forces a search of frame alignment. subsequent reframe commands must have this bit in the 0 state first. 3 tfm1 transparent framing mode 1. a 1 forces the transmit framer to pass system data unmodified to the line and the receive framer to pass line data unmodified to the system. the receive framer is forced not to align to the input receive data. ds1: register frm_pr43 bit 2bit 0 must be set to 000. the f bit is located in time slot 0, bit 7. the transmit framer extracts bit 7 of time slot 0 from rchidata and places this bit in the f-bit position of the transmit line data. the receive framer inserts the bit in the f-bit position of the receive line data into time slot 0, bit 7 of the tchidata. cept: rchidata time slot 0 is inserted into time slot 0 of the transmit line data. receive line time slot 0 is inserted into time slot 0 of tchidata. 4 tfm2 transparent framing mode 2. a 1 forces the transmit framer to pass system data unmodified to the line. the receive framer functions normally as programmed. ds1: register frm_pr43 bit 2bit 0 must be set to 000. the f bit is located in time slot 0, bit 7. the transmit framer extracts bit 7 of time slot 0 from rchidata and places this bit in the f-bit position of the transmit line data. cept: rchidata time slot 0 is inserted into time slot 0 of the transmit line data. 5 sysfsm system frame sync mask. a 1 masks the system frame synchronization signal in the transmit framer section. note : the transmit framer must see at least one valid system synchronization pulse to initialize its counts; afterwards, this bit may be set. for those applications that have jitter on the transmit clock signal relative to the system clock signal, enable this bit so that the jitter is isolated from the transmit framer. 67 reserved. write to 0. lucent technologies inc. 175 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. framer register architecture (continued) automatic and manual transmission of the remote frame alarm control register (frm_pr27) the default value of this register is 00 (hex). table 155. transmission of remote frame alarm and cept automatic transmission of a bit = 1 control register (frm_pr27) (67b, c7b) bit symbol description 0arlfa automatic remote frame alarm on lfa (arlfa). a 1 transmits the remote frame alarm to the line whenever the receive framer detects loss of frame alignment (rlfa). 1 aab16lmfa automatic a bit on lmfa (cept only). a 1 transmits a = 1 to the line whenever the receive framer detects loss of time slot 16 signaling multiframe alignment (rts16lmfa). 2 aab0lmfa automatic a bit on lmfa (cept only). a 1 transmits a = 1 to the line whenever the receive framer detects loss of time slot 0 multiframe alignment (rts0lmfa). 3atmrx automatic a bit on crc-4 multiframe reframer timer expiration (cept only). a 1 transmits a = 1 to the line when the receive framer detects the expiration of either the 100 ms or 400 ms timers due to loss of multiframe alignment. 4 aarsa6_8 automatic a bit on rsa6_8 (cept only). a 1 transmits a = 1 to the line whenever the receive framer detects the sa6 = 1000 pattern. 5 aarsa6_c automatic a bit on rsa6_c (cept only). a 1 transmits a = 1 to the line whenever the receive framer detects the sa6 = 1100 pattern. 6tjrfa transmit d4 japanese remote frame alarm. a 1 transmits a valid japanese remote frame alarm for the d4 frame format. 7trfa transmit remote frame alarm. a 1 transmits a valid remote frame alarm for the corre- sponding frame format. preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 176 lucent technologies inc. lucent technologies inc. framer register architecture (continued) automatic and manual transmission of e bit = 0 control register the default value of this register is 00 (hex). table 156. cept automatic transmission of e bit = 0 control register (frm_pr28) (67c; c7c) * whenever bits (e.g., si, sa, etc.) are transmitted from the system transparently, frm_pr29 must first be momentarily written t o 001xxxxx (binary). otherwise, the transmit framer will not be able to locate the biframe alignment. bit symbol description 0sis si-bit source. in cept with no crc-4 mode, a 1 transmits tsif and tsinf in the si bit position to the line in fas and not fas, respectively. a 0, in non-crc-4 mode, trans- mits system si data to the line transparently*. t1e transmit one e = 0. in cept with crc-4 mode, a 0 transmits e = tsif in frame 13 and e = tsinf in frame 15. a 1 transmits one e bit = 0 for each write access to tsif = 0 or tsinf = 0. 1tsif transmit bit 1 in fas. in cept with no crc-4, this bit can be transmitted to the line in bit 1 of the fas. in crc-4 mode, this bit is used for e-bit data in frame 13. 2tsinf transmit bit 1 in not fas. in cept with no crc-4, this bit can be transmitted to the line in bit 1 of the not fas. in crc-4 mode, this bit is used for e-bit data in frame 15. 3 atercrce automatic transmit e bit = 0 for received crc-4 errored events. a 1 transmits e = 0 to the line whenever the receive framer detects a crc-4 errored checksum. 4atelts0mfa automatic transmit e bit = 0 for received loss of crc-4 multiframe alignment. a 1 transmits e = 0 to the line whenever the receive framer detects a loss of crc-4 multi- frame alignment condition. 5atertx automatic transmit e bit = 0 on expiration of cept crc-4 loss of multiframe timer. a 1 transmits e = 0 to the line whenever the receive framer detects the expiration of either the 100 ms or 400 ms timer due to the loss of crc-4 multiframe alignment. 67 these bits are zero. lucent technologies inc. 177 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. framer register architecture (continued) sa4sa8 source register (frm_pr29) these bits contain the fixed transmit sa bits and define the source of the sa bits. the default value of this register is 00 (hex). table 157. sa4sa8 source register (frm_pr29) (67d; c7d) table 158. sa bits source control for bit 5bit 7 in frm_pr29 * whenever bits (e.g., si, sa, etc.) are transmitted from the system transparently, frm_pr29 must first be momentarily written t o 001xxxxx (binary). otherwise, the transmit framer will not be able to locate the biframe alignment. bit symbol description 04 tsa4tsa8 transmit sa4sa8 bit. 57 sas5sas7 sa source control bits[2:0]. sas7 sas6 sas5 function 1 0 0 a single sa bit, selected in register frm_pr43, is sourced from either the external transmit facility data input port tfdl (frm_pr21 bit 6 = 1) or from the internal fdl- hdlc block (frm_pr21 bit 6 = 0). the remaining sa bits are sourced by this register bit 0bit 4 if enabled in register frm_pr30, or transparently from the system inter- face*. 1 0 1 a single sa bit, selected in register frm_pr43, is sourced from either the external transmit facility data input port tfdl (frm_pr21 bit 6 = 1) or from the internal fdl- hdlc block (frm_pr21 bit 6 = 0). the remaining sa bits are transmitted transpar- ently from the system interface*. 1 1 x a single sa bit, selected in register frm_pr43, is sourced from either the external transmit facility data input port tfdl (frm_pr21 bit 6 = 1) or from the internal fdl- hdlc block (frm_pr21 bit 6 = 0). the remaining sa bits are sourced from the trans- mit sa stack registers (frm_pr31frm_pr40) if enabled in register frm_pr30, or transparently from the system interface*. 01x slc -96 mode. tr a n s m i t slc -96 stack and the slc -96 interrupts are enabled. the slc -96 fdl bits are sourced from the transmit slc -96 stack, registers frm_pr31 frm_pr40. cept mode. transmit sa stack and the sa interrupts are enabled. the sa bits are sourced from the transmit sa stack (frm_pr31frm_pr40) if enabled in register frm_pr30, or transparently from the system interface*. 0 0 1 sa[4:8] bits are transmitted from the system interface transparently through the framer*. 0 0 0 sa[4:8] bits are sourced by bit 0bit 4 of this register if enabled in register frm_pr30, or transparently from the system interface*. preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 178 lucent technologies inc. lucent technologies inc. framer register architecture (continued) sa4sa8 control register (frm_pr30) in conjunction with frm_pr29 bit 5bit 7, these bits define the source of the individual sa4sa8 bits. the default value of this register is 00 (hex). table 159. sa4sa8 control register (frm_pr30) (67e; c7e) sa transmit stack register (frm_pr31frm_pr40) in cept frame format, registers frm_pr31frm_pr40 are used to program the sa bits in the cept multiframe not-fas words. if crc-4 is enabled, this data is transmitted to the line synchronously to the crc-4 multiframe. the default value of these registers is 00 (hex). table 160. sa transmit stack (frm_pr31frm_pr40) ((67f688); (c7fc88)) bit symbol description 04 tesa4tesa8 transparent enable sa4sa8 bit mask. a 1 enables the transmission of the cor- responding sa bits from the sa source register (frm_pr29 bit 0bit 4) or from the transmit sa stack. a 0 allows the corresponding sa bit to be transmitted transpar- ently from the system interface. 56 reserved. write to 0. 7 tdnf transmit double notfas system time slot. a 0 enables the transmission of the fas and notfas on the tchidata interface. a 1 enables the notfas to be trans- mitted twice on the tchidata interface, and the received time slot 0 from the rchi- data is assumed to carry notfas data that is repeated twice. register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 frm_pr31 sa4-1 sa4-3 sa4-5 sa4-7 sa4-9 sa4-11 sa4-13 sa4-15 frm_pr32 sa4-17 sa4-19 sa4-21 sa4-23 sa4-25 sa4-27 sa4-29 sa4-31 frm_pr33 sa5-1 sa5-3 sa5-5 sa5-7 sa5-9 sa5-11 sa5-13 sa5-15 frm_pr34 sa5-17 sa5-19 sa5-21 sa5-23 sa5-25 sa5-27 sa5-29 sa5-31 frm_pr35 sa6-1 sa6-3 sa6-5 sa6-7 sa6-9 sa6-11 sa6-13 sa6-15 frm_pr36 sa6-17 sa6-19 sa6-21 sa6-23 sa6-25 sa6-27 sa6-29 sa6-31 frm_pr37 sa7-1 sa7-3 sa7-5 sa7-7 sa7-9 sa7-11 sa7-13 sa7-15 frm_pr38 sa7-17 sa7-19 sa7-21 sa7-23 sa7-25 sa7-27 sa7-29 sa7-31 frm_pr39 sa8-1 sa8-3 sa8-5 sa8-7 sa8-9 sa8-11 sa8-13 sa8-15 frm_pr40 sa8-17 sa8-19 sa8-21 sa8-23 sa8-25 sa8-27 sa8-29 sa8-31 lucent technologies inc. 179 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. register architecture (continued) slc -96 transmit stack (frm_pr31frm_pr40) in slc -96 frame format, registers frm_pr31frm_pr35 are used to source the transmit facility data link bits in the f s bit positions. the default value of these registers is 00 (hex). table 16 1 . slc -96 transmit stack (frm_pr31frm_pr40) ((67f688); (c7fc88)) in slc -96 frame format, the bits in registers frm_pr31frm_pr35 are transmitted using the format shown in table 164. table 162. transmit slc -96 fdl format cept time slot 16 x-bit remote multiframe alarm and ais control register (frm_pr41) the default value of this register is 00 (hex). table 163. cept time slot 16 x-bit remote multiframe alarm and ais control register (frm_pr41) (689; c89) register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 frm_pr31 0 0 x-0 x-0 x-0 x-1 x-1 x-1 frm_pr32 0 0 x-0 x-0 x-0 x-1 x-1 x-1 frm_pr33 xc 1 xc 2 xc 3 xc 4 xc 5 xc 6 xc 7 xc 8 frm_pr34 xc 9 xc 10 xc 11 xspb 1 = 0 xspb 2 = 1 xspb 3 = 0 xm 1 xm 2 frm_pr35 xm 3 xa 1 xa 2 xs 1 xs 2 xs 3 xs 4 xspb 4 = 1 frm_pr36 frm_pr40 00 000000 fs = 000111000111 xc1 xc2 xc3 xc4 xc5 xc6 xc7 xc8 xc9 xc10 xc11 xspb1 xspb2 xspb3 xm1 xm2 xm3 xa1 xa2 xs1 xs2 xs3 xs4 xspb4 bit symbol description 02 tts16x0tts16x2 transmit time slot 16 x0x2 bits. the content of these bits are written into cept signaling multiframe time slot 16 x bits. 3xs x-bit source. a 1 enables the tts16x[2:0] bits to be written into cept time slot 16 signaling multiframe frame. a 0 transmits the x bits transparently. 4 altts16rmfa automatic line transmit time slot 16 remote multiframe alarm. a 1 enables the transmission of cept time slot 16 signaling remote multiframe alarm when the receive framer is in the loss of cept signaling (rts16lmfa) state. 5tlts16rmfa transmit line time slot 16 remote multiframe alarm. a 1 enables the trans- mission of cept time slot 16 signaling remote multiframe alarm. 6tlts16ais transmit line time slot 16 ais. a 1 enables the transmission of cept time slot 16 alarm indication signal. 7 reserved. write to 0. preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 180 lucent technologies inc. lucent technologies inc. framer register architecture (continued) framer exercise register (frm_pr42) this register is used for exercising the device in a test mode. in normal operation, it and should be set to 00 (hex). the default value of this register is 00 (hex). table 164. framer exercise register (frm_pr42) (68a; c8a) table 165 . framer exercises, frm_pr42 bit 5bit 0 (68a; c8a) bit description fex0fex5 framer exercise bits 05 (fex0fex5). see table 167. fex6 fex7 second pulse interval. 001 second pulse. 0 1 500 ms pulse. 1 0 100 ms pulse. 11reserved. exercise type fex5 fex4 fex3 fex2 fex1 fex0 exercise framing format facility status 0 0 1 0 0 0 line format violation all crc checksum error esf or cept receive remote frame alarm d4 or esf 0 0 1 0 0 1 alarm indication signal detection all loss of frame alignment cept receive remote frame alarm japanese d4 0 0 1 0 1 0 time slot 0 1-bit shift cept transmit corrupt crc esf & cept 0 0 1 0 1 1 frame-bit error & loss of frame align- ment all loss of time slot 16 multiframe align- ment cept remote frame alarm d4 & dds crc bit errors esf & cept 0 0 1 1 0 0 frame-bit errors all 0 0 1 1 0 1 frame-bit errors & loss of frame alignment all loss of time slot 16 multiframe align- ment cept 0 0 1 1 1 0 frame-bit error & loss of frame align- ment all change of frame alignment esf, dds & cept loss of time slot 16 multiframe align- ment cept 0 0 1 1 1 1 excessive crc checksum errors esf & cept 0 0 0 0 0 0 no test mode activated lucent technologies inc. 181 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. framer register architecture (continued) table 165. framer exercises, frm_pr42 bit 5bit 0 (68a; c8a) (continued) ds1 system interface control and cept fdl source control register (frm_pr43) the default value of this register is 00 (hex). table 166. ds1 system interface control and cept fdl source control register (frm_pr43) (68b; c8b) exercise type fex5 fex4 fex3 fex2 fex1 fex0 exercise framing format performance status 0 1 0 0 0 0 errored second all 0 1 0 0 0 1 bursty errored second 0 1 0 0 1 0 severely errored second 0 1 0 0 1 1 severely errored second count 0 1 0 1 0 0 unavailable state 0 1 0 1 0 1 factory test 0 1 0 1 1 0 increment status counters sr6sr14 0 1 0 1 1 1 increment status counters sr6sr14 status counters 1 0 0 0 0 1 crc error counter all 1 0 0 0 1 0 errored event counter 1 0 x 0 1 1 errored second counter 1 0 0 1 0 0 severely errored second counter 1 0 0 1 0 1 unavailable second counter 1 0 0 1 1 0 line format violation counter 1 0 0 1 1 1 frame bit error counter all other combinations reserved bit symbol description 02 sts0sts2 in ds1 mode, bit 0bit 2 program the positions of the stuffed time slots on the chi. the content of the stuffed time slot can be programmed using register frm_pr23. bits 210 000 = sdddsdddsdddsdddsdddsdddsdddsddd 001 = dsdddsdddsdddsdddsdddsdddsdddsdd 010 = ddsdddsdddsdddsdddsdddsdddsdddsd 011 = dddsdddsdddsdddsdddsdddsdddsddds 100 = ddddddddddddddddddddddddssssssss safdl0 safdl2 in cept mode, bit 0bit 2 program the sa bit source of the facility data link. bits 210 000: sa4 = fdl 001: sa5 = fdl 010: sa6 = fdl 011: sa7 = fdl 100: sa8 = fdl in both ds1 and cept modes, only the bit values shown above may be selected. 3ssc slc -96 signaling control (ds1 only). a 1 enables the slc -96 9-state signaling mode. a 0 enables 16-state signaling in the slc -96 framing mode. 47 reserved. write to 0. preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 182 lucent technologies inc. lucent technologies inc. framer register architecture (continued) signaling mode register (frm_pr44) this register programs various signaling modes. the default value is 00 (hex). table 167. signaling mode register (frm_pr44) (68c; c8c) bit symbol description 0tsig transparent signaling. a 0 enables signaling information to be inserted into and extracted from the data stream. the signaling source is either the signaling registers or the system data (in the associated signaling mode). in ds1 modes, the choice of data or voice channels assignment for each channel is a function of the programming of the f and g bits in the transmit signaling registers. a 1 enables data to pass through the device transparently. all channels are treated as data channels. 1stomp stomp mode. a 0 allows the received signaling bits to pass through the receive signal- ing circuit unmodified. in ds1 robbed-bit signaling modes, a 1 enables the receive sig- naling circuit to replace (in those time slots programmed for signaling) all signaling bits (in the receive line bit stream) with a 1, after extracting the valid signaling information. in cept time slot 16 signaling modes, a 1 enables the received signaling circuit substitute of the signaling combination of abcd = 0000 to abcd = 1111. 2asm associated signaling mode. a 1 enables the associate signaling mode which config- ures the chi to carry both data and its associated signaling information. enabling this mode must be in conjunction with the programming of the chi data rate to 4.096 mbits/s or 8.192 mbit/s. each channel consists of 16 bits where 8 bits are data and the remaining 8 bits are signaling information. 3rsi receive signaling inhibit. a 1 inhibits updating of the receive signaling buffer. 4mos message-oriented signaling. ds1: a 1 enables the channel 24 message-oriented sig- naling mode. 5 tsr-asm tsr-asm mode (ds1 only). in the ds1 mode, setting this bit and frm_pr44 bit 2 (asm) to 1 enables the transmit signaling register f and g bits to define the robbed-bit signaling format while the abcd bit information is extracted from the chi interface. the f and g bits are copied to the receive signaling block and are used to extract the signal- ing information from the receive line. 6astsais automatic system transmit signaling ais (cept only). a 1 transmits ais in system time slot 16 during receive loss of time slot 16 signaling multiframe alignment state. 7tcss transmit cept system signaling squelch (cept only). ais is transmitted in time slot 16 of the transmit system data. lucent technologies inc. 183 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. framer register architecture (continued) chi common control register (frm_pr45) these bits define the common attributes of the chi for tchidata, tchidatab, rchidata, and rchdatab. the default value of this register is 00 (hex). table 168. chi common control register (frm_pr45) (68d; c8d) bit symbol description 0hflf high-frequency/low-frequency pllck clock mode. a 0 enables the low-frequency pllck mode for the divide down circuit in the internal phase-lock loop section (ds1 pllck = 1.544 mhz; cept pllck = 2.048 mhz). the divide down circuit will produce an 8 khz signal on div-pllck, pin 6 and pin 32. a 1 enables the high-frequency pllck mode for the divide down circuit in the internal phase-lock loop section (ds1: pllck = 6.176 (4 x 1.544) mhz; cept: 8.192 (4 x 2.048) mhz). the divide down circuit will pro- duce a 32 khz signal on div-pllck. 1cms concentration highway clock mode. a 0 enables the chi clock frequency and chi data rate to be equal. function fo cms =1 is reserved. this control bit affects both the transmit and receive interfaces. 23 cdrs0 cdrs1 concentration highway interface data rate select. bits chi data rate 23 0 0 2.048 mbits/s 0 1 4.096 mbits/s 1 0 8.192 mbits/s 11 reserved 4chimm concentration highway master mode. a 0 enables external systems frame synchroni- zation signal (tchifs) to drive the transmit path of the framers concentration highway interface. a 1 enables the framers transmit concentration interface to generate a system frame synchronization signal derived from the receive line interface. the framers system frame synchronization signal is generated on the tchifs output pin. applications using the receive line clock as the reference clock signal of the system are recommended to enable this mode and use the tchifs signal generated by the framer. the receive chi path is not affected by this mode. 56 reserved. write to 0. 7 hwyen highway enable. a 1 in this bit position enables transmission to the concentration high- way. this allows the T7630 to be fully configured before transmission to the highway. a 0 forces the idle code as defined in register frm_pr22 to be transmitted to the line in all payload time slots and the transmit chi pin is forced to a high-impedance state for all chi transmitted time slots. preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 184 lucent technologies inc. lucent technologies inc. framer register architecture (continued) chi common control register (frm_pr46) this register defines the common attributes of the transmit and receive chi. the default value is 00 (hex). table 169. chi common control register (frm_pr46) (68e; c8e) chi transmit control register (frm_pr47) the default value of this register is 00 (hex). table 170. chi transmit control register (frm_pr47) (68f; c8f) chi receive control register (frm_pr48) the default value of this register is 00 (hex). table 171. chi receive control register (frm_pr48) (690; c90) bit symbol description 02 toff0 toff2 transmit chi bit offset. these 3 bits define the bit offset from tchifs for each trans- mit time slot. the offset is the number of tchick clock periods by which the first bit is delayed from tchifs. 3tfe transmit frame clock edge. a 0 (1) enables the falling (rising) edge of tchick to latch in the frame synchronization signal, tchifs. 46 roff0 roff2 receive chi bit offset. these 3 bits define the bit offset from rchifs for each received time slot. the offset is the number of rchick clock periods by which the first bit is delayed from rchifs. 7rfe received frame clock edge. a 0 (1) enables the falling (rising) edge of rchick to latch in the frame synchronization signal, rchifs. bit symbol description 05 tbyoff0 tbyoff5 transmit byte offset. combined with frm_pr65 bit 0 (tbyoff6), these 6 bits define the byte offset from tchifs to the beginning of the next transmit chi frame on tchi- data. 6tce transmitter clock edge. a 1 (0) enables the rising (falling) edge of tchick to clock out data on tchidata. 7 reserved. write to 0. bit symbol description 05 rbyoff0 rbyoff5 receiver byte offset. combined with frm_pr66 bit 0 (rbyoff6), these 6 bits define the byte offset from rchifs to the beginning of the next receive chi frame on rchi- data. 6 rce receiver clock edge. a 1 (0) enables the rising (falling) edge of rchick to latch data on rchidata. 7 reserved. write to 0. lucent technologies inc. 185 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. framer register architecture (continued) chi transmit time-slot enable registers (frm_pr49frm_pr52) these four registers define which transmit chi time slots are enabled. a 1 enables the tchidata or tchidatab time slot. a 0 forces the chi transmit highway time slot to be 3-stated. the default value of this register is 00 (hex). table 172. chi transmit time-slot enable registers (frm_pr49frm_pr52) ((691694); (c91c94)) chi receive time-slot enable registers (frm_pr53frm_pr56) these four registers define which receive chi time slots are enabled. a 1 enables the rchidata or rchidatab time slots. a 0 disables the time slot and transmits the programmable idle code of register frm_pr22 to the line in the corresponding time slot. the default value of this register is ff (hex). table 173. chi receive time-slot enable registers (frm_pr53frm_pr56) ((695698); (c95c98)) chi transmit highway select registers (frm_pr57frm_pr60) these four registers define which transmit chi highway tchidata or tchidatab contains valid data for the active time slot. a 0 enables tchidata, and a 1 enables tchidatab. the default value of this register is 00 (hex). table 174. chi transmit highway select registers (frm_pr57frm_pr60) ((69969c); (c99c9c)) register bit symbol description frm_pr49 70 ttse31ttse24 transmit time-slot enable bits 3124. frm_pr50 70 ttse23ttse16 transmit time-slot enable bits 2316. frm_pr51 70 ttse15ttse8 transmit time-slot enable bits 158. frm_pr52 70 ttse7ttse0 transmit time-slot enable bits 70. register bit symbol description frm_pr53 70 rtse31rtse24 receive time-slot enable bits 3124. frm_pr54 70 rtse23rtse16 receive time-slot enable bits 2316. frm_pr55 70 rtse15rtse8 receive time-slot enable bits 158. frm_pr56 70 rtse7rtse0 receive time-slot enable bits 70. register bit symbol description frm_pr57 70 ths31ths24 transmit highway select bits 3124. frm_pr58 70 ths23ths16 transmit highway select bits 2316. frm_pr59 70 ths15ths8 transmit highway select bits 158. frm_pr60 70 ths7ths0 transmit highway select bits 70. preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 186 lucent technologies inc. lucent technologies inc. framer register architecture (continued) chi receive highway select registers (frm_pr61frm_pr64) these four registers define which receive chi highway rchidata or rchidatab contains valid data for the active time slot. a 0 enables rchidata, and a 1 enables rchidatab. the default value of these registers is 00 (hex). table 175. chi receive highway select registers (frm_pr61frm_pr64) ((69d6a0); (c9dca0)) chi transmit control register (frm_pr65) the default value of this register is 00 (hex). table 176. chi transmit control register (frm_pr65) (6a1; ca1) chi receive control register (frm_pr66) the default value of this register is 00 (hex). table 177. chi receive control register (frm_pr66) (6a2; ca2) reserved parameter/control registers registers frm_pr67 and frm_pr68, addresses 6a3 and 6a4 or ca3 and ca4, are reserved. write these regis- ters to 0. register bit symbol description frm_pr61 70 rhs31rhs24 receive highway select bits 3124. frm_pr62 70 rhs23rhs16 receive highway select bits 2316. frm_pr63 70 rhs15rhs8 receive highway select bits 158. frm_pr64 70 rhs7rhs0 receive highway select bits 70. bit symbol description 0 tbyoff6 transmit chi 64-byte offset. a 1 enables a 64-byte offset from tchifs to the begin- ning of the next transmit chi frame on tchidata. a 0 enables a 0-byte offset (if bit 0 bit 5 of frm_pr47 = 0). combing bit 0bit 5 of frm_pr47 with this bit allows program- ming the byte offset from 0127. 1 tchidts transmit chi double time-slot mode. a 1 enables the transmit chi double time-slot mode. in this mode, the tchi clock runs at twice the rate of tchidata. 27 reserved. write to 0. bit symbol description 0 rbyoff6 receive chi 64-byte offset. a 1 enables a 64-byte offset from rchifs to the begin- ning of the next receive chi frame on rchidata. a 0 enables a 0-byte offset (if bit 0 bit 5 of frm_pr48 = 0). combing bit 0bit 5 of frm_pr48 with this bit allows program- ming the byte offset from 0127. 1 rchidts receive chi double time-slot mode. a 1 enables the transmit chi double time-slot mode. in this mode, the rchi clock runs at twice the rate of rchidata. 27 reserved. write to 0. lucent technologies inc. 187 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. framer register architecture (continued) auxiliary pattern generator control register (frm_pr69) the following register programs the auxiliary pattern generator in the transmit framer. the default value of this reg- ister is 00 (hex). table 178. auxiliary pattern generator control register (frm_pr69) (6a5; ca5) * * to generate test pattern signals using this register, register frm_pr20 must be set to 00 (hex). bit symbol description 0itd invert transmit data. setting this bit to 1 inverts the transmitted pattern. 1tpei test pattern error insertion. toggling this bit from a 0 to a 1 inserts a single bit error in the transmitted test pattern. 2 gblksel generator block select. setting this bit to 1 enables the generation of test patterns in this reg- ister. 3gfrmsel generator frame test pattern. setting this bit to 1 results in the generation of an unframed pattern. a 0 results in a framed pattern (t1 and cept). 4 7 gptrn0 gptrn3 generator pattern select. these 4 bits select which random pattern is to be transmitted. bits 7654 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 description mark (all ones) (ais) qrss (2 20 C 1 with zero suppression) 2 5 C 1 63 (2 6 C 1) 511 (2 9 C 1) 511 (2 9 C 1) reversed 2047 (2 11 C 1) 2047 (2 11 C 1) reversed 2 15 C 1 2 20 C 1 2 20 C 1 2 23 C 1 1:1 (alternating) generator polynomial 1+x C17 +x C20 1+x C3 +x C5 1+x C1 +x C6 1+x C5 +x C9 1+x C4 +x C9 1+x C9 +x C11 1+x C2 +x C11 1+x C14 +x C15 1+x C3 +x C20 1+x C17 +x C20 1+x C18 +x C23 standard o.151 o.153 o.152 o.151 o.153 cb113/cb114 o.151 preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 188 lucent technologies inc. lucent technologies inc. framer register architecture (continued) pattern detector control register (frm_pr70) the following register programs the pattern detector in the receive framer. the default value of this register is 00 (hex). table 179. pattern detector control register (frm_pr70) (6a6; ca6) * * to generate/detect test pattern signals using this register, register frm_pr20 must be set to 00 (hex). bit symbol description 0ird invert receive data. setting this bit to 1 enables the pattern detector to detect the inverse of the selected pattern. 1 reserved. write to 0. 2 dblksel detector block select. setting this bit to 1 enables the detection of test patterns in this regis- ter. 3duftp detect unframed test pattern. setting this bit to 1 results in the search for an unframed pat- tern. a 0 results in a search for a framed pattern (t1 and cept). 4 7 dptrn0 dptrn3 detector pattern select. these 4 bits select which random pattern is to be transmitted. bits 7654 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 description mark (all ones) (ais) qrss (2 20 C 1 with zero suppression) 2 5 C 1 63 (2 6 C 1) 511 (2 9 C 1) 511 (2 9 C 1) reversed 2047 (2 11 C 1) 2047 (2 11 C 1) reversed 2 15 C 1 2 20 C 1 2 20 C 1 2 23 C 1 1:1 (alternating) generator polynomial 1+x C17 +x C20 1+x C3 +x C5 1+x C1 +x C6 1+x C5 +x C9 1+x C4 +x C9 1+x C9 +x C11 1+x C2 +x C11 1+x C14 +x C15 1+x C3 +x C20 1+x C17 +x C20 1+x C18 +x C23 standard o.151 o.153 o.152 o.151 o.153 cb113/cb114 o.151 lucent technologies inc. 189 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. framer register architecture (continued) transmit signaling registers: ds1 format (frm_tsr0frm_tsr23) these registers program the transmit signaling registers for the ds1 and cept mode. the default value of these registers is 00 (hex). table 180. transmit signaling registers: ds1 format (frm_tsr0frm_tsr23) ((6e06f7); (ce0cf7)) transmit signaling registers: cept format (frm_tsr0frm_tsr31) table 181. transmit signaling registers: cept format (frm_tsr0frm_tsr31) ((6e06ff); (ce0cff)) * in pcs0 or pcs1 signaling mode, this bit is undefined. transmit signal registers bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ds1 transmit signaling registers (023) p g f x d c b a esf format: voice channel with 16-state signaling slc -96: 9-state signaling (depending on the setting in register frm_pr43) x00xdcba voice channel with 4-state signaling x 0 1 x x x b a voice channel with 2-state signaling x 1 1 x x x a a data channel (no signaling) x 1 0 x x x x x transmit signal registers bit 7 bit 65 bit 4 * bit 3 bit 2 bit 1 bit 0 frm_tsr1frm_tsr15 p x e[1:15] d[1:15] c[1:15] b[1:15] a[1:15] frm_tsr17frm_tsr31 p x e[17:31] d[17:31] c[17:31] b[17:31] a[17:31] preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 190 lucent technologies inc. lucent technologies inc. fdl register architecture regbank4 and regbank7 contain the status and programmable control registers for the facility data link chan- nels fdl1 and fdl2, respectively. the base address for regbank4 is 800 (hex) and for regbank7 is e00 (hex). within these register banks, the bit map is identical for both fdl1 and fdl2. the register bank architecture for fdl1 and fdl2 is shown in table 184. the register bank consists of 8-bit regis- ters classified as either (programmable) parameter registers or status registers. default values are shown in paren- theses. table 182. fdl register set (80080e); (e00e0e) fdl register [address (hex)] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 fdl_pr0[800;e00] fransit3 (1) fransit2 (0) fransit1 (1) fransit0 (0) reserved (0) reserved (0) flags (0) fdint (0) fdl_pr1[801;e01] ftprm (0) frpf (0) ftr (0) frr (0) fte (0) fre (0) fllb (0) frlb (0) fdl_pr2[802;e02] ftbcrc (0) friie (0) frovie (0) freofie (0) frfie (0) ftundie (0) fteie (0) ftdie (0) fdl_pr3[803;e03] ftfc (0) ftabt (0) ftil5 (0) ftil4 (0) ftil3 (0) ftil2 (0) ftil1 (0) ftil0 (0) fdl_pr4[804;e04] ftd7 (0) ftd6 (0) ftd5 (0) ftd4 (0) ftd3 (0) ftd2 (0) ftd1 (0) ftd0 (0) fdl_pr5[805;e05] ftic7 (0) ftic6 (0) ftic5 (0) ftic4 (0) ftic3 (0) ftic2 (0) ftic1 (0) ftic0 (0) fdl_pr6[806;e06] fransie (0) afdlbpm (0) fril5 (0) fril4 (0) fril3 (0) fril2 (0) fril1 (0) fril0 (0) fdl_pr8[808;e08] frmc7 (0) frmc6 (0) frmc5 (0) frmc4 (0) frmc3 (0) frmc2 (0) frmc1 (0) frmc0 (0) fdl_pr9[809;e09] reserved (0) ftm (0) fmatch (0) faloct (0) fmstat (0) foctof2 (0) foctof1 (0) foctof0 (0) fdl_pr10[80a;e0a] ftansi (0) reserved (0) ftansi5 (0) ftansi4 (0) ftansi3 (0) ftansi2 (0) ftansi1 (0) ftansi0 (0) fdl_sr0[80b;e0b] fransi fridl frouerun freof frf ftundabt ftem ftdone fdl_sr1[80c;e0c] fted ftqs6 ftqs5 ftqs4 ftqs3 ftqs2 ftqs1 ftqs0 fdl_sr2[80d;e0d] freof frqs6 frqs5 frqs4 frqs3 frqs2 frqs1 frqs0 fdl_sr3[80e;e0e] 0 0 x5 x4 x3 x2 x1 x0 fdl_sr4[807;e0f] frd7 frd6 frd5 frd4 frd3 frd2 frd1 frd0 lucent technologies inc. 191 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. fdl parameter/control registers (80080e; e00e0e) these registers define the mode configuration of each framer unit. these registers are initially set to a default value upon a hardware reset. these registers are all read/write registers. default states of all bits in this register group are also indicated in the parameter/control register map. table 183. fdl configuration control register (fdl_pr0) (800; e00) * the fransit bits (fdl_pr0 bits 47) must be changed only following an fdl reset or when the fdl is idle. table 184. fdl control register (fdl_pr1) (801; e01) bit symbol description 0 fdint dynamic interrupt. fdint = 0 causes multiple occurrences of the same event to gener- ate a single interrupt before the interrupt bit is cleared by reading register fdl_sr0. fdint = 1 causes multiple interrupts to be generated. this bit should normally be set to 0. 1flags flags. flags = 0 forces the transmission of the idle pattern (11111111) in the absence of transmit fdl information. flags = 1 forces the transmission of the flag pattern (01111110) in the absence of transmit fdl information. this bit resets to 0. 23 reserved. write to 0. 47 fransit0 fransit3 receive ansi bit code threshold. these bits define the number of esf ansi bit codes needed for indicating a valid code. the default is ten (1010 (binary))*. bit symbol description 0frlb remote loopback. frlb = 1 loops the received facility data back to the transmit facility data interface. this bit resets to 0. 1 fllb local loopback. fllb = 1 loops transmit facility data back to the receive facility data link interface. the receive facility data link information from the framer interface is ignored. this bit resets to 0. 2fre fdl receiver enable. fre = 1 activates the fdl receiver. fre = 0 forces the fdl receiver into an inactive state. this bit resets to 0. 3 fte fdl transmitter enable. fte = 1 activates the fdl transmitter. fte = 0 forces the fdl transmitter into an inactive state. this bit resets to 0. 4frr fdl receiver reset. frr = 1 generates an internal pulse that resets the fdl receiver. the fdl receiver fifo and related circuitry are cleared. the freof, frf, fridl, and overrun interrupts are cleared. this bit resets to 0. 5ftr fdl transmitter reset. ftr = 1 generates an internal pulse that resets the fdl trans- mitter. the fdl transmit fifo and related circuitry are cleared. the ftundabt bit is cleared, and the ftem interrupt is set; the ftdone bit is forced to 0 in the hdlc mode and forced to 1 in the transparent mode. this bit resets to 0. 6frpf fdl receive prm frames. frpf = 1 allows the receive fdl unit to write the entire receive performance report message including the frame header and crc data into the receive fdl fifo. this bit resets to 0. 7 ftprm transmit prm enable. when this bit is set, the receive framer will write into the transmit fdl fifo its performance report message data. the current second of this data is stored in the receive framers status registers. the receive framers prm is transmitted once per second. the prm is followed by either idles or flags transmitted after the prm. when this bit is 0, the transmit fdl expects data from the microprocessor interface. preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 192 lucent technologies inc. lucent technologies inc. fdl parameter/control registers (80080e; e00e0e) (continued) table 185. fdl interrupt mask control register (fdl_pr2) (802; e02) bit symbol description 0 ftdie fdl transmit-done interrupt enable. when this interrupt enable bit is set, an interrupt pin transition is generated after the last bit of the closing flag or abort sequence is sent. in the transparent mode (register fdl_pr9 bit 6 = 1), an interrupt pin transition is generated when the transmit fifo is completely empty. ftdie is cleared upon reset. 1 fteie fdl transmitter-empty interrupt enable. when this interrupt-enable bit is set, an interrupt pin transition is generated when the transmit fifo has reached the pro- grammed empty level (see register fdl_pr3). fteie is cleared upon reset. 2 ftundie fdl transmit underrun interrupt enable. when this interrupt-enable bit is set, an interrupt pin transition is generated when the transmit fifo has underrun. ftundie is cleared upon reset and is not used in the transparent mode. 3frfie fdl receiver-full interrupt enable. when this interrupt-enable bit is set, an interrupt pin transition is generated when the receive fifo has reached the pro- grammed full level (see register fdl_pr6). frfie is cleared upon reset. 4freofie fdl receive end-of-frame interrupt enable. when this interrupt-enable bit is set, an interrupt pin transition is generated when an end-of-frame is detected by the fdl receiver. freofie is cleared upon reset and is not used in the transparent mode. 5frovie fdl receiver overrun interrupt enable. when this interrupt-enable bit is set, an interrupt pin transition is generated when the receive fifo overruns. frovie is cleared upon reset. 6 friie fdl receiver idle-interrupt enable. when this interrupt-enable bit is set, an interrupt pin transition is generated when the receiver enters the idle state. friir is cleared upon reset and is not used in the transparent mode. 7 ftbcrc fdl transmit bad crc. setting this bit to 1 forces bad crcs to be sent on all transmit- ted frames (for test purposes) until the ftbcrc bit is cleared to 0. lucent technologies inc. 193 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. fdl parameter/control registers (80080e; e00e0e) (continued) table 186. fdl transmitter configuration control register (fdl_pr3) (803; e03) 1. do not set ftabt = 1 and ftfc = 1 at the same time. table 187. fdl transmitter fifo register (fdl_pr4) (804; e04) table 188. fdl transmitter idle character register (fdl_pr5) (805; e05) bit symbol description 05 ftil0ftil5 fdl transmitter interrupt level. these bits specify the minimum number of empty positions in the transmit fifo which triggers a transmitter-empty (ftem) interrupt. encoding is in binary; bit 0 is the least significant bit. a code of 001010 will generate an interrupt when the transmit fifo has ten or more empty locations. the code 000000 generates an interrupt when the transmit fifo is empty. the number of empty transmit fifo locations is obtained by reading the transmit fdl status register fdl_sr1. 6 1 ftabt fdl transmitter abort. ftabt = 1 forces the transmit fdl unit to abort the frame at the last user data byte waiting for transmission. when the transmitter reads the byte tagged with ftabt, the abort sequence (01111111) is transmitted in its place. a full byte is guar- anteed to be transmitted. once set for a specific data byte, the internal ftabt status cannot be cleared by writing to this bit. clearing this bit has no effect on a previously writ- ten ftabt. the last value written to ftabt is available for reading. 7 1 ftfc fdl transmitter frame complete. ftfc = 1 forces the transmit fdl unit to terminate the frame normally after the last user data byte is written to the transmit fifo. the crc sequence and a closing flag are appended. ftfc should be set to 1 within 1 ms of writ- ing the last byte of the frame in the transmit fifo. when the transmit fifo is empty, writ- ing two data bytes to the fifo before setting ftcf provides a minimum of 1 ms to write ftfc = 1. once set for a specific data byte, the internal ftfc status bit cannot be cleared by writing to this bit. clearing this bit has no effect on a previously written ftfc. the last value written to ftfc is available for reading. bit symbol description 07 ftd0ftd7 fdl transmit data. the user data to be transmitted via the fdl block are loaded through this register. bit symbol description 07 ftic0 ftic7 fdl transmitter idle character. this character is used only in transparent mode (regis- ter fdl_pr9 bit 6 = 1). when the pattern match bit (register fdl_pr9 bit 5) is set to 1, the fdl transmit unit sends this character whenever the transmit fifo is empty. the default is to send the ones idle character, but any character can be programmed by the user. preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 194 lucent technologies inc. lucent technologies inc. fdl parameter/control registers (80080e; e00e0e) (continued) table 189. fdl receiver interrupt level control register (fdl_pr6) (806; e06) table 190. fdl register fdl_pr7 table 191. fdl receiver match character register (fdl_pr8) (808; e08) bit symbol description 05 fril0fril5 fdl receive interrupt level. bit 0bit 5 define receiver fifo full threshold value that will generate the corresponding frf interrupt. fril = 000000 forces the receive fdl fifo to generate an interrupt when the receive fifo is completely full. fril = 001111 will force the receive fdl fifo to generate an interrupt when the receive fifo contains 15 or more bytes. 6 reserved. write to 0. 7 fransie fdl receiver ansi bit codes interrupt enable. if this bit is set to 1, an interrupt pin condition is generated whenever a valid ansi code is received. bit symbol description 07 reserved. bit symbol description 07 frmc0 frmc7 receiver fdl match character. this character is used only in transparent mode (regis- ter fdl_pr9 bit 6 = 1). when the pattern match bit (register fdl_pr9 bit 5) is set to 1, the receive fdl unit searches the incoming bit stream for the receiver match character. data is loaded into the receive fifo only after this character has been identified. the byte identified as matching the receiver match character is the first byte loaded into the receive fifo. the default is to search for a flag, but any character can be programmed by the user. the search for the receiver match character can be in a sliding window fash- ion (register fdl_pr9 bit 4 = 0) or only on byte boundaries (register fdl_pr9 bit 4 = 1). lucent technologies inc. 195 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. fdl parameter/control registers (80080e; e00e0e) (continued) table 192. fdl transparent control register (fdl_pr9) (809; e09) * the octet boundary is relative the first receive clock edge after the receiver has been enabled (enr, fdl_pr1 bit 2 = 1). table 193. fdl transmit ansi esf bit codes (fdl_pr10) (80a; e0a) bit symbol description 02 foctof0 foctof2 fdl octet offset (read only). these bits record the offset relative to the octet bound- ary when the receive character was matched. the foctof bits are valid when register fdl_pr9 bit 3 (fmstat) is set to 1. a value of 111 (binary) indicates byte alignment. 3fmstat match status (read only). when this bit is set to 1 by the receive fdl unit, the receiver match character has been recognized. the octet offset status bits (fdl_pr9 bit[2:0]) indicates the offset relative to the octet boundary* at which the receive character was matched. if no match is being performed (register fdl_pr9 bit 5 = 0), the fmstat bit is set to 1 automatically when the first byte is received, and the octet offset status bits (reg- ister fdl_pr9 bit 0bit 2) are set to 111 (binary). 4faloct frame-sync align. when this bit is set to 1, the receive fdl unit searches for the receive match character (fdl-pr8) only on an octet boundary. when this bit is 0, the receive fdl unit searches for the receive match character in a sliding window fashion. 5fmatch pattern match. fmatch affects both the transmitter and receiver. when this bit is set to 1, the fdl does not load data into the receive fifo until the receive match character programmed in register fdl_pr8 has been detected. the search for the receive match character is in a sliding window fashion if register fdl_pr9 bit 4 is 0, or only on octet boundaries if register fdl_pr9 bit 4 is set to 1. when this bit is 0, the receive fdl unit loads the matched byte and all subsequent data directly into the receive fifo. on the transmit side, when this bit is set to 1 the transmitter sends the transmit idle character programmed into register fdl_pr5 when the transmit fifo has no user data. the default idle is to transmit the hdlc ones idle character (ff hexadecimal); however, any value can be used by programming the transmit idle character register fdl_pr5. if this bit is 0, the transmitter sends ones idle characters when the transmit fifo is empty. 6 ftm fdl transparent mode. when this bit is set to 1, the fdl unit performs no hdlc pro- cessing on incoming or outgoing data. 7 reserved. write to 0. bit symbol description 05 ftansi0 ftansi5 fdl esf bit-oriented message data. the transmit esf fdl bit messages are in the form 111111110x 0 x 1 x 2 x 3 x 4 x 5 0, where the order of transmission is from left to right. 6 reserved. write to 0. 7ftansi transmit ansi bit codes. when this bit is set to 1, the fdl unit will continuously trans- mit the ansi code defined using register fdl_pr10 bit 0bit 5 as the esf bit code messages. this bit must stay high long enough to ensure the ansi code is sent at least 10 times. preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 196 lucent technologies inc. lucent technologies inc. fdl parameter/control registers (80080e; e00e0e) (continued) table 194. fdl interrupt status register (clear on read) (fdl_sr0) (80b; e0b) * if an fdl receive fifo overrun occurs, as indicated by register fdl_sr0 bit 5 (froverun) = 1, the fdl must be reset to restore proper operation of the fifo. following an fdl receive fifo overrun, data extracted prior to the required reset may be corrupted. bit symbol description 0 ftdone transmit done. this status bit is set to 1 when transmission of the current fdl frame has been completed, either after the last bit of the closing flag or after the last bit of an abort sequence. in the transparent mode (fdl_pr9 bit 6 = 1), this status bit is set when the transmit fifo is completely empty. a hardware interrupt is generated only if the cor- responding interrupt-enable bit (fdl_pr2 bit 0) is set. this status bit is cleared to 0 by a read of this register. 1 ftem transmitter empty. if this bit is set to 1, the fdl transmit fifo is at or below the pro- grammed depth. a hardware interrupt is generated only if the corresponding interrupt- enable bit (fdl_pr2 bit 1) is set. if dint (fdl_pr0 bit 0) is 0, this status bit is cleared by a read of this register. if fdint (fdl_pr0 bit 0) is set to 1, this bit actually represents the dynamic transmit empty condition, and is cleared to 0 only when the transmit fifo is loaded above the programmed empty level. 2 ftundabt fdl transmit underrun abort. a 1 indicates that an abort was transmitted because of a transmit fifo underrun. a hardware interrupt is generated only if the corresponding interrupt-enable bit (fdl_pr2 bit 2) is set. this status bit is cleared to 0 by a read of this register. this bit must be cleared to 0 before further transmission of data is allowed. this interrupt is not generated in the transparent mode. 3frf fdl receiver full. this bit is set to 1 when the receive fifo is at or above the pro- grammed full level (fdl_pr6). a hardware interrupt is generated if the corresponding interrupt-enable bit (fdl_pr2 bit 3) is set. if fdint (fdl_pr0 bit 0) is 0, this status bit is cleared to 0 by a read of this register. if fdint (fdl_pr0 bit 0) is set to 1, then this bit is cleared only when the receive fifo is read (or emptied) below the programmed full level*. 4freof fdl receive end of frame. this bit is set to 1 when the receiver has finished receiving a frame. it becomes 1 upon reception of the last bit of the closing flag of a frame or the last bit of an abort sequence. a hardware interrupt is generated only if the corresponding interrupt-enable bit (fdl_pr2 bit 4) is set. this status bit is cleared to 0 by a read of this register. this interrupt is not generated in the transparent mode. 5froverun fdl receiver overrun. this bit is set to 1 when the receive fifo has overrun its capacity. a hardware interrupt is generated only if the corresponding interrupt-enable bit (fdl_pr2 bit 5) is set. this status bit is cleared to 0 by a read of this register*. 6 fridl fdl receiver idle. this bit is set to 1 when the fdl receiver is idle (i.e., 15 or more consecutive ones have been received). a hardware interrupt is generated only if the cor- responding interrupt-enable bit (fdl_pr2 bit 6) is set. this status bit is cleared to 0 by a read of this register. this interrupt is not generated in the transparent mode. 7 fransi fdl receive ansi bit codes. this bit is set to 1 when the fdl receiver recognizes a valid t1.403 esf fdl bit code. the receive ansi bit code is stored in register fdl_sr3. an interrupt is generated only if the corresponding interrupt enable of register fdl_pr6 bit 7 = 1. this status bit is cleared to 0 by a read this register. lucent technologies inc. 197 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. fdl parameter/control registers (80080e; e00e0e) (continued) table 195. fdl transmitter status register (fdl_sr1) (80c; e0c) * the count of fdl_sr1 bits 06 includes sf byte. table 196. fdl receiver status register (fdl_sr2) (80d; e0d) * immediately following an fdl reset, the value in bit 0bit 6 of this status register is 0. after the initial read of the fdl r eceive fifo, the value in bit 0bit 6 of this status register is the number of bytes including sf byte that may be read from the fifo. received fdl ansi bit codes status register (fdl_sr3) the 6-bit code extracted from the ansi code 111111110x 0 x 1 x 2 x 3 x 4 x 5 0 is stored in this register. table 197. receive ansi fdl status register (fdl_sr3) (80e; e0e) receive fdl fifo register (fdl_sr4) this fifo stores the received fdl data. only valid fifo bytes indicated in register fdl_sr2 may be read. read- ing nonvalid fifo locations or reading the fifo when it is empty will corrupt the fifo pointer and will require an fdl reset to restore proper fdl operation. table 198. fdl receiver fifo register (fdl_sr4) (807; e07) bit symbol description 06 ftqs0 ftqs6 fdl transmit queue status. bit 0bit 6 indicate how many bytes can be added to the transmit fifo*. the bits are encoded in binary where bit 0 is the least significant bit. 7 fted fdl transmitter empty dynamic. fted = 1 indicates that the number of empty loca- tions available in the transmit fifo is greater than or equal to the value programmed in the ftil bits (fdl_pr3). bit symbol description 06 frqs0 frqs6 fdl receive queue status. bit 0bit 6 indicate how many bytes are in the receive fifo, including the first status of frame (sf) byte. the bits are encoded in binary where bit 0 is the least significant bit*. 7feof fdl end of frame. when feof = 1, the receive queue status indicates the number of bytes up to and including the first sf byte. b7 b6 b5 b4 b3 b2 b1 b0 0 0 x5 x4 x3 x2 x1 x0 bit symbol description 07 frd0frd7 fdl receive data. the user data received via the fdl block are read through this register. preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 198 lucent technologies inc. lucent technologies inc. register maps global registers table 199. global register set line interface unit parameter/control and status registers table 200. line interface unit register set * * the logic value in parentheses below each bit definition is the default state upon completion of hardware reset. ? these bits must be written to 1. reg clear-on- read (cor) read (r) write (w) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register address (hexadecimal) greg0 cor reserved (0) fdl2int (0) frmr2int (0) liu2int (0) reserved (0) fdl1int (0) frmr1int (0) liu1int (0) 000 greg1 r/w reserved (0) fdl2ie (0) frmr2ie (0) liu2ie (0) reserved (0) fdl1ie (0) frmr1ie (0) liu1ie (0) 001 greg2 r/w tid2-rsd1 (0) tsd2-rsd1 (0) tid1-rsd1 (0) tsd1-rsd1 (0) tsd2-rid1 (0) tid2-rid1 (0) tsd1-rid1 (0) tid1-rid1 (0) 002 greg3 r/w tid1-rsd2 (0) tsd1-rsd2 (0) tid2-rsd2 (0) tsd2-rsd2 (0) tsd1-rid2 (0) tid1-rid2 (0) tsd2-rid2 (0) tid2-rid2 (0) 003 greg4 r/w reserved (0) alie (0) secctrl (0) reserved (0) t1-r2 (0) t2-r1 (0) reserved (0) reserved (0) 004 greg5 r 0111 01 1 0 005 greg6 r 0 0 1 1 0 0 0 0 006 greg7 r 0000 00 1 0 007 liu_reg clear-on- read (cor) read (r) write (w) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register address (hexadecimal) framer 1 framer 2 liu_reg0 cor reserved reserved reserved reserved lotc tdm dlos alos 400 a00 liu_reg1 r/w reserved (0) reserved (0) reserved (0) reserved (0) lotcie (0) tdmie (0) dlosie (0) alosie (0) 401 a01 liu_reg2 r/w reserved (0) reserved (0) restart (0) highz (0) reserved (0) losstd (0) reserved (0) reserved (0) 402 a02 liu_reg3 r/w reserved ? (1) reserved ? (1) reserved ? (1) lossd (0) dual (0) code (1) jat (0) jar (0) 403 a03 liu_reg4 r/w reserved (0) reserved (0) jabw0 (0) phizalm (0) prlalm (0) pflalm (0) rcvais (0) altimer (0) 404 a04 liu_reg5 r/w reserved (0) reserved (0) reserved (0) reserved (0) loopa (0) loopb (0) xlais (1) pwrdn (0) 405 a05 liu_reg6 r/w reserved (0) reserved (0) reserved (0) reserved (0) reserved (0) eq2 (0,ds1) (1,cept) eq1 (0,ds1) (1,cept) eq0 (0) 406 a06 lucent technologies inc. 199 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. register maps (continued) framer parameter/control registers (read-write) table 201. framer unit status register map * unbracketed contents are valid for ds1 modes. bracketed contents, [], are valid for cept mode. framer status clear-on- read (cor) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register address (hexadecimal) framer 1 framer 2 frm_sr0 cor s96sr 0 rssfe tssfe ese fae rac fac 600 c00 frm_sr1 cor ais auxp rts16ais lbfa lfalr ltsfa lt s 0 m fa lsfa lt s 1 6 m fa lfa 601 c01 frm_sr2 cor rsa6 = f rsa6 = e rsa6 = c rsa6 = a rsa6 = 8 crebit rjya rts16mfa rfa 602 c02 frm_sr3 cor slipu slipo lcrcatmx rebit ece crce fbe lfv 603 c03 frm_sr4 cor fdl-llboff tsasr fdl-llbon rsasr fdl-plboff fdl-plbon llbon cma llboff bfa ssfa nfa 604 c04 frm_sr5 cor etreuas etreses etrebes etrees etuas etses etbes etes 605 c05 frm_sr6 cor ntreuas ntreses ntrebes ntrees ntuas ntses ntbes ntes 606 c06 frm_sr7 cor rquasi rpseudo ptrnber detect nrouas nt1ouas erouas ouas 607 c07 frm_sr8 cor bpv15 bpv14 bpv13 bpv12 bpv11 bpv10 bpv9 bpv8 608 c08 frm_sr9 cor bpv7 bpv6 bpv5 bpv4 bpv3 bpv2 bpv1 bpv0 609 c09 frm_sr10 cor fe15 fe14 fe13 fe12 fe11 fe10 fe9 fe8 60a c0a frm_sr11 cor fe7 fe6 fe5 fe4 fe3 fe2 fe1 fe0 60b c0b frm_sr12 cor cec15 cec14 cec13 cec12 cec11 cec10 cec9 cec8 60c c0c frm_sr13 cor cec7 cec6 cec5 cec4 cec3 cec2 cec1 cec0 60d c0d frm_sr14 cor rec15 rec14 rec13 rec12 rec11 rec10 rec9 rec8 60e c0e frm_sr15 cor rec7 rec6 rec5 rec4 rec3 rec2 rec1 rec0 60f c0f frm_sr16 cor cnt15 cnt14 cnt13 cnt12 cnt11 cnt10 cnt9 cnt8 610 c10 frm_sr17 cor cnt7 cnt6 cnt5 cnt4 cnt3 cnt2 cnt1 cnt0 611 c11 frm_sr18 cor ent15 ent14 ent13 ent12 ent11 ent10 ent9 ent8 612 c12 frm_sr19 cor ent7 ent6 ent5 ent4 ent3 ent2 ent1 ent0 613 c13 frm_sr20 cor etes15 etes14 etes13 etes12 etes11 etes10 etes9 etes8 614 c14 frm_sr21 cor etes7 etes6 etes5 etes4 etes3 etes2 etes1 etes0 615 c15 frm_sr22 cor etbes15 etbes14 etbes13 etbes12 etbes11 etbes10 etbes9 etbes8 616 c16 frm_sr23 cor etbes7 etbes6 etbes5 etbes4 etbes3 etbes2 etbes1 etbes0 617 c17 frm_sr24 cor etses15 etses14 etses13 etses12 etses11 etses10 etses9 etses8 618 c18 frm_sr25 cor etses7 etses6 etses5 etses4 etses3 etses2 etses1 etses0 619 c19 frm_sr26 cor etus15 etus14 etus13 etus12 etus11 etus10 etus9 etus8 61a c1a frm_sr27 cor etus7 etus6 etus5 etus4 etus3 etus2 etus1 etus0 61b c1b frm_sr28 cor etrees15 etrees14 etrees13 etrees12 etrees11 etrees10 etrees9 etrees8 61c c1c frm_sr29 cor etrees7 etrees6 etrees5 etrees4 etrees3 etrees2 etrees1 etrees0 61d c1d frm_sr30 cor etrebes15 etrebes14 etrebes13 etrebes12 etrebes11 etrebes10 etrebes9 etrebes8 61e c1e frm_sr31 cor etrebes7 etrebes6 etrebes5 etrebes4 etrebes3 etrebes2 etrebes1 etrebes0 61f c1f frm_sr32 cor etreses15 etreses14 etreses13 etreses12 etreses11 etreses10 etreses9 etreses8 620 c20 frm_sr33 cor etreses7 etreses6 etreses5 etreses4 etreses3 etreses2 etreses1 etreses0 621 c21 frm_sr34 cor etreus15 etreus14 etreus13 etreus12 etreus11 etreus10 etreus9 etreus8 622 c22 frm_sr35 cor etreus7 etreus6 etreus5 etreus4 etreus3 etreus2 etreus1 etreus0 623 c23 preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 200 lucent technologies inc. lucent technologies inc. register maps (continued) table 201. framer unit status register map (continued) * unbracketed contents are valid for ds1 modes. bracketed contents, [], are valid for cept mode. framer status clear-on- read (cor) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register address (hexadecimal) framer 1 framer 2 frm_sr36 cor ntes15 ntes14 ntes13 ntes12 ntes11 ntes10 ntes9 ntes8 624 c24 frm_sr37 cor ntes7 ntes6 ntes5 ntes4 ntes3 ntes2 ntes1 ntes0 625 c25 frm_sr38 cor ntbes15 ntbes14 ntbes13 ntbes12 ntbes11 ntbes10 ntbes9 ntbes8 626 c26 frm_sr39 cor ntbes7 ntbes6 ntbes5 ntbes4 ntbes3 ntbes2 ntbes1 ntbes0 627 c27 frm_sr40 cor ntses15 ntses14 ntses13 ntses12 ntses11 ntses10 ntses9 ntses8 628 c28 frm_sr41 cor ntses7 ntses6 ntses5 ntses4 ntses3 ntses2 ntses1 ntses0 629 c29 frm_sr42 cor ntus15 ntus14 ntus13 ntus12 ntus11 ntus10 ntus9 ntus8 62a c2a frm_sr43 cor ntus7 ntus6 ntus5 ntus4 ntus3 ntus2 ntus1 ntus0 62b c2b frm_sr44 cor ntrees15 ntrees14 ntrees13 ntrees12 ntrees11 ntrees10 ntrees9 ntrees8 62c c2c frm_sr45 cor ntrees7 ntrees6 ntrees5 ntrees4 ntrees3 ntrees2 ntrees1 ntrees0 62d c2d frm_sr46 cor ntrebes15 ntrebes14 ntrebes13 ntrebes12 ntrebes11 ntrebes10 ntrebes9 ntrebes8 62e c2e frm_sr47 cor ntrebes7 ntrebes6 ntrebes5 ntrebes4 ntrebes3 ntrebes2 ntrebes1 ntrebes0 62f c2f frm_sr48 cor ntreses15 ntreses14 ntreses13 ntreses12 ntreses11 ntreses10 ntreses9 ntreses8 630 c30 frm_sr49 cor ntreses7 ntreses6 ntreses5 ntreses4 ntreses3 ntreses2 ntreses1 ntreses0 631 c31 frm_sr50 cor ntreus15 ntreus14 ntreus13 ntreus12 ntreus11 ntreus10 ntreus9 ntreus8 632 c32 frm_sr51 cor ntreus7 ntreus6 ntreus5 ntreus4 ntreus3 ntreus2 ntreus1 ntreus0 633 c33 frm_sr52 cor nfb1 [fi5e] fbi [fi3e] a bit sa4 sa5 sa6 sa7 sa8 634 c34 frm_sr53cor00000rx2rx1rx0635c35 frm_sr54 * cor 0 [sa4-1] 0 [sa4-3] r-0 [sa4-5] r-0 [sa4-7] r-0 [sa4-9] r-1 [sa4-11] r-1 [sa4-13] r-1 [sa4-15] 636 c36 frm_sr55 * cor 0 [sa4-17] 0 [sa4-19] r-0 [sa4-21] r-0 [sa4-23] r-0 [sa4-25] r-1 [sa4-27] r-1 [sa4-29] r-1 [sa4-31] 637 c37 frm_sr56 * cor rc1 [sa5-1] rc2 [sa5-3] rc3 [sa5-5] rc4 [sa5-7] rc5 [sa5-9] rc6 [sa5-11] rc7 [sa5-13] rc8 [sa5-15] 638 c38 frm_sr57 * cor rc9 [sa5-17] rc10 [sa5-19] rc11 [sa5-21] rspb1 = 0 [sa5-23] rspb2 = 1 [sa5-25] rspb3 = 0 [sa5-27] rm1 [sa5-29] rm2 [sa5-31] 639 c39 frm_sr58 * cor rm3 [sa6-1] ra1 [sa6-3] ra2 [sa6-5] rs1 [sa6-7] rs2 [sa6-9] rs3 [sa6-11] rs4 [sa613] rspb4 = 1 [sa6-15] 63a c3a frm_sr59 * cor 0 [sa6-17] 0 [sa6-19] 0 [sa6-21] 0 [sa6-23] 0 [sa6-25] 0 [sa6-27] 0 [sa6-29] 0 [sa6-31] 63b c3b frm_sr60 * cor 0 [sa7-1] 0 [sa7-3] 0 [sa7-5] 0 [sa7-7] 0 [sa7-9] 0 [sa7-11] 0 [sa7-13] 0 [sa7-15] 63c c3c frm_sr61 * cor 0 [sa7-17] 0 [sa7-19] 0 [sa7-21] 0 [sa7-23] 0 [sa7-25] 0 [sa7-27] 0 [sa7-29] 0 [sa7-31] 63d c3d frm_sr62 * cor g3 [sa8-1] lv [sa8-3] g4 [sa8-5] u1 [sa8-7] u2 [sa8-9] g5 [sa8-11] sl [sa8-13] g6 [sa8-15] 63e c3e frm_sr63 * cor fe [sa8-17] se [sa8-19] lb [sa8-21] g1 [sa8-23] r [sa8-25] g2 [sa8-27] nm [sa8-29] nl [sa8-31] 63f c3f lucent technologies inc. 201 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. register maps (continued) receive framer signaling registers (read-only) table 202. receive signaling registers map * in the ds1 robbed-bit signaling modes, these bits are copied from the corresponding transmit signaling registers. in the cept signaling modes, these bits are in the 0 state and should be ignored. ? in the ds1 signaling modes, these registers contain unknown data. ? in ds1 4-state and 2-state signaling, these bits contain unknown data. in ds1 2-state signaling, these bits contain unknown data. ** in the cept signaling modes, the a-, b-, c-, d-, and p-bit information of these registers contains unknown data. ?? signifies unknown data. receive signaling read (r) bit 7 bit 6 * bit 5 * bit 4 ? bit 3 ? bit 2 ? bit 1 bit 0 register address (hexadecimal) framer 1 framer 2 frm_rsr0 ** r p g_0f_0e_0d_0c_0b_0a_0 640 c40 frm_rsr1 r p g_1 f_1 e_1 d_1 c_1 b_1 a_1 641 c41 frm_rsr2 r p g_2 f_2 e_2 d_2 c_2 b_2 a_2 642 c42 frm_rsr3 r p g_3 f_3 e_3 d_3 c_3 b_3 a_3 643 c43 frm_rsr4 r p g_4 f_4 e_4 d_4 c_4 b_4 a_4 644 c44 frm_rsr5 r p g_5 f_5 e_5 d_5 c_5 b_5 a_5 645 c45 frm_rsr6 r p g_6 f_6 e_6 d_6 c_6 b_6 a_6 646 c46 frm_rsr7 r p g_7 f_7 e_7 d_7 c_7 b_7 a_7 647 c47 frm_rsr8 r p g_8 f_8 e_8 d_8 c_8 b_8 a_8 648 c48 frm_rsr9 r p g_9 f_8 e_8 d_8 c_8 b_8 a_8 649 c49 frm_rsr10 r p g_10 f_10 e_10 d_10 c_10 b_10 a_10 64a c4a frm_rsr11 r p g_11 f_11 e_11 d_11 c_11 b_11 a_11 64b c4b frm_rsr12 r p g_12 f_12 e_12 d_12 c_12 b_12 a_12 64c c4c frm_rsr13 r p g_13 f_13 e_13 d_13 c_13 b_13 a_13 64d c4d frm_rsr14 r p g_14 f_14 e_14 d_14 c_14 b_14 a_14 64e c4e frm_rsr15 r p g_15 f_15 e_15 d_15 c_15 b_15 a_15 64f c4f frm_rsr16 ?? r p g_16 f_16 e_16 d_16 c_16 b_16 a_16 650 c50 frm_rsr17 r p g_17 f_17 e_17 d_17 c_17 b_17 a_17 651 c51 frm_rsr18 r p g_18 f_18 e_18 d_18 c_18 b_18 a_18 652 c52 frm_rsr19 r p g_19 f_19 e_19 d_19 c_19 b_19 a_19 653 c53 frm_rsr20 r p g_20 f_20 e_20 d_20 c_20 b_20 a_20 654 c54 frm_rsr21 r p g_21 f_21 e_21 d_21 c_21 b_21 a_21 655 c55 frm_rsr22 r p g_22 f_22 e_22 d_22 c_22 b_22 a_22 656 c56 frm_rsr23 r p g_23 f_23 e_23 d_23 c_23 b_23 a_23 657 c57 frm_rsr24 ? rpx ?? x e_24 d_24 c_24 b_24 a_24 658 c58 frm_rsr25 ? r p x x e_25 d_25 c_25 b_25 a_25 659 c59 frm_rsr26 ? r p x x e_26 d_26 c_26 b_26 a_26 65a c5a frm_rsr27 ? r p x x e_27 d_27 c_27 b_27 a_27 65b c5b frm_rsr28 ? r p x x e_28 d_28 c_28 b_28 a_28 65c c5c frm_rsr29 ? r p x x e_29 d_29 c_29 b_29 a_29 65d c5d frm_rsr30 ? r p x x e_30 d_30 c_30 b_30 a_30 65e c5e frm_rsr31 ? r p x x e_31 d_31 c_31 b_31 a_31 65f c5f preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 202 lucent technologies inc. lucent technologies inc. register maps (continued) framer unit parameter register map table 203. framer unit parameter register map framer control read (r) write (w) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register address (hexadecimal) framer 1 framer 2 frm_pr0 r/w slcie (0) reserved (0) rsrie (0) tsrie (0) sr567ie (0) sr34ie (0) sr2ie (0) sr1ie (0) 660 c60 frm_pr1 r/w sr1b7ie (0) sr1b6ie (0) sr1b5ie (0) sr1b4ie (0) sr1b3ie (0) sr1b2ie (0) sr1b1ie (0) sr1b0ie (0) 661 c61 frm_pr2 r/w sr2b7ie (0) sr2b6ie (0) sr2b5ie (0) sr2b4ie (0) sr2b3ie (0) sr2b2ie (0) sr2b1ie (0) sr2b0ie (0) 662 c62 frm_pr3 r/w sr3b7ie (0) sr3b6ie (0) sr3b5ie (0) sr3b4ie (0) sr3b3ie (0) sr3b2ie (0) sr3b1ie (0) sr3b0ie (0) 663 c63 frm_pr4 r/w sr4b7ie (0) sr4b6ie (0) sr4b5ie (0) sr4b4ie (0) sr4b3ie (0) sr4b2ie (0) sr4b1ie (0) sr4b0ie (0) 664 c64 frm_pr5 r/w sr5b7ie (0) sr5b6ie (0) sr5b5ie (0) sr5b4ie (0) sr5b3ie (0) sr5b2ie (0) sr5b1ie (0) sr5b0ie (0) 665 c65 frm_pr6 r/w sr6b7ie (0) sr6b6ie (0) sr6b5ie (0) sr6b4ie (0) sr6b3ie (0) sr6b2ie (0) sr6b1ie (0) sr6b0ie (0) 666 c66 frm_pr7 r/w sr7b7ie (0) sr7b6ie (0) sr7b5ie (0) sr7b4ie (0) sr7b3ie (0) sr7b2ie (0) sr7b1ie (0) sr7b0ie (0) 667 c67 frm_pr8 r/w lc2 (1) lc1 (1) lc0 (0) fmode4 (0) fmode3 (0) fmode2 (0) fmode1 (0) fmode0 (0) 668 c68 frm_pr9 r/w crco7 (0) crco6 (0) crco5 (0) crco4 (0) crco3 (0) crco2 (0) crco1 (0) crco0 (0) 669 c69 frm_pr10 r/w esm1 (0) esm0 (0) reserved (0) reserved (0) cnuclben (0) feren (0) aism (0) ssa6m (0) 66a c6a frm_pr11 r/w est7 (0) est6 (0) est5 (0) est4 (0) est3 (0) est2 (0) est1 (0) est0 (0) 66b c6b frm_pr12 r/w sest15 (0) sest14 (0) sest13 (0) sest12 (0) sest11 (0) sest10 (0) sest9 (0) sest8 (0) 66c c6c frm_pr13 r/w sest7 (0) sest6 (0) sest5 (0) sest4 (0) sest3 (0) sest2 (0) sest1 (0) sest0 (0) 66d c6d frm_pr14 r/w 0 0 0 0 etslip (0) etais (0) etlmfa (0) etlfa (0) 66e c6e frm_pr15 r/w etresa6-f (0) etresa6-e (0) etresa6-8 (0) etrerfa (0) etreslip (0) etreais (0) etrelmfa (0) etrelfa (0) 66f c6f frm_pr16 r/w ntsa6-c (0) 0ntsa6-8 (0) 0ntslip (0) ntais (0) ntlmfa (0) ntlfa (0) 670 c70 frm_pr17 r/w 0 0 0 ntrerfa (0) ntreslip (0) ntreais (0) ntrelmfa (0) ntrelfa (0) 671 c71 frm_pr18 r/w 0 0 0 0 ntresa6-c (0) ntresa6-f (0) ntresa6-e (0) ntresa6-8 (0) 672 c72 frm_pr19 r/w afdplbe (0) afdllbe (0) reserved (0) allbe (0) tsais (0) reserved (0) asaistmx (0) asais (0) 673 c73 frm_pr20 r/w ticrc (0) tlic (0) tllboff (0) tllbon (0) tqrs (0) tprs (0) tufauxp (0) tufais (0) 674 c74 lucent technologies inc. 203 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. register maps (continued) table 203. framer unit parameter register map (continued) framer control read (r) write (w) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register address (hexadecimal) framer 1 framer 2 frm_pr21 r/w tc/r = 1 (0) tfdlc (0) tfdlsais (0) tfdllais (0) reserved (0) reserved (0) reserved (0) reserved (0) 675 c75 frm_pr22 r/w tlic7 (0) tlic6 (1) tlic5 (1) tlic4 (1) tlic3 (1) tlic2 (1) tlic1 (1) tlic0 (1) 676 c76 frm_pr23 r/w sstsc7 (0) sstsc6 (1) sstsc5 (1) sstsc4 (1) sstsc3 (1) sstsc2 (1) sstsc1 (1) sstsc0 (1) 677 c77 frm_pr24 r/w lbc2 (0) lbc1 (0) lbc0 (0) tslba4 (0) tslba3 (0) tslba2 (0) tslba1 (0) tslba0 (0) 678 c78 frm_pr25 r/w reserved (0) slbc1 (0) slbc0 (0) stslba4 (0) stslba3 (0) stslba2 (0) stslba1 (0) stslba0 (0) 679 c79 frm_pr26 r/w reserved (0) reserved (0) sysfsm (0) tfm2 (0) tfm1 (0) frfrm (0) swre- start (0) swreset (0) 67a c7a frm_pr27 r/w trfa (0) tjrfa (0) aarsa6_c (0) aarsa6_8 (0) atmx (0) aab0lmfa (0) aab16lmfa (0) arlfa (0) 67b c7b frm_pr28 r/w 0 0 atertx (0) atelts0mfa (0) atecrce (0) tsinf (0) tsif (0) sis, t1e (0) 67c c7c frm_pr29 r/w sas7 (0) sas6 (0) sas5 (0) tsa8 (0) tsa7 (0) tsa6 (0) tsa5 (0) tsa4 (0) 67d c7d frm_pr30 r/w tdnf (0) reserved (0) reserved (0) tesa8 (0) tesa7 (0) tesa6 (0) tesa5 (0) tesa4 (0) 67e c7e frm_pr31 r/w 0 sa4-1 0 sa4-3 x-0 sa4-5 x-0 sa4-7 x-0 sa4-9 x-1 sa4-11 x-1 sa4-13 x-1 sa4-15 67f c7f frm_pr32 r/w 0 sa4-17 0 sa4-19 x-0 sa4-21 x-0 sa4-23 x-0 sa4-25 x-1 sa4-27 x-1 sa4-29 x-1 sa4-31 680 c80 frm_pr33 r/w xc1 sa5-1 xc2 sa5-3 xc3 sa5-5 xc4 sa5-7 xc5 sa5-9 xc6 sa5-11 xc7 sa5-13 xc8 sa5-15 681 c81 frm_pr34 r/w xc9 sa5-17 xc10 sa5-19 xc11 sa5-21 xspb1 = 0 sa5-23 xspb2 = 1 sa5-25 xspb3 = 0 sa5-27 xm1 sa5-29 xm2 sa5-31 682 c82 frm_pr35 r/w xm3 sa6-1 xa1 sa6-3 xa2 sa6-5 xs1 sa6-7 xs2 sa6-9 xs3 sa6-11 xs4 sa613 xspb4 = 1 sa6-15 683 c83 frm_pr36 r/w sa6-17 sa6-19 sa6-21 sa6-23 sa6-25 sa6-27 sa6-29 sa6-31 684 c84 frm_pr37 r/w sa7-1 sa7-3 sa7-5 sa7-7 sa7-9 sa7-11 sa7-13 sa7-15 685 c85 frm_pr38 r/w sa7-17 sa7-19 sa7-21 sa7-23 sa7-25 sa7-27 sa7-29 sa7-31 686 c86 frm_pr39 r/w sa8-1 sa8-3 sa8-5 sa8-7 sa8-9 sa8-11 sa8-13 sa8-15 687 c87 frm_pr40 r/w sa8-17 sa8-19 sa8-21 sa8-23 sa8-25 sa8-27 sa8-29 sa8-31 688 c88 frm_pr41 r/w reserved (0) tlts16ais (0) tlts16rmfa (0) altts16rmfa (0) xs (0) tts16x2 (0) tts16x1 (0) tts16x0 (0) 689 c89 preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 204 lucent technologies inc. lucent technologies inc. register maps (continued) table 203. framer unit parameter register map (continued) framer control read (r) write (w) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register address (hexadecimal) framer 1 framer 2 frm_pr42 r/w fex7 (0) fex6 (0) fex5 (0) fex4 (0) fex3 (0) fex2 (0) fex1 (0) fex0 (0) 68a c8a frm_pr43 r/w reserved (0) reserved (0) reserved (0) reserved (0) ssc (0) sts2 [safdl2] (0) sts1 [safdl1] (0) sts0 [safdl0] (1) 68b c8b frm_pr44 r/w tcss (0) astsais (0) tsr-asm (0) mos (0) rsi (0) asm (0) stomp (0) tsig (0) 68c c8c frm_pr45 r/w hwyen (0) reserved (0) reserved (0) chimm (0) cdrs1 (0) cdrs0 (0) cms (0) hflf (0) 68d c8d frm_pr46 r/w rfe (0) roff2 (0) roff1 (0) roff0 (0) tfe (0) toff2 (0) toff1 (0) toff0 (0) 68e c8e frm_pr47 r/w reserved (0) tce (0) tbyoff5 (0) tbyoff4 (0) tbyoff3 (0) tbyoff2 (0) tbyoff1 (0) tbyoff0 (0) 68f c8f frm_pr48 r/w reserved (0) rce (0) rbyoff5 (0) rbyoff4 (0) rbyoff3 (0) rbyoff2 (0) rbyoff1 (0) rbyoff0 (0) 690 c90 frm_pr49 r/w ttse31 (0) ttse30 (0) ttse29 (0) ttse28 (0) ttse27 (0) ttse26 (0) ttse25 (0) ttse24 (0) 691 c91 frm_pr50 r/w ttse23 (0) ttse22 (0) ttse21 (0) ttse20 (0) ttse19 (0) ttse18 (0) ttse17 (0) ttse16 (0) 692 c92 frm_pr51 r/w ttse15 (0) ttse14 (0) ttse13 (0) ttse12 (0) ttse11 (0) ttse10 (0) ttse9 (0) ttse8 (0) 693 c93 frm_pr52 r/w ttse7 (0) ttse6 (0) ttse5 (0) ttse4 (0) ttse3 (0) ttse2 (0) ttse1 (0) ttse0 (0) 694 c94 frm_pr53 r/w rtse31 (0) rtse30 (0) rtse29 (0) rtse28 (0) rtse27 (0) rtse26 (0) rtse25 (0) rtse24 (0) 695 c95 frm_pr54 r/w rtse23 (0) rtse22 (0) rtse21 (0) rtse20 (0) rtse19 (0) rtse18 (0) rtse17 (0) rtse16 (0) 696 c96 frm_pr55 r/w rtse15 (0) rtse14 (0) rtse13 (0) rtse12 (0) rtse11 (0) rtse10 (0) rtse9 (0) rtse8 (0) 697 c97 frm_pr56 r/w rtse7 (0) rtse6 (0) rtse5 (0) rtse4 (0) rtse3 (0) rtse2 (0) rtse1 (0) rtse0 (0) 698 c98 frm_pr57 r/w ths31 (0) ths30 (0) ths29 (0) ths28 (0) ths27 (0) ths26 (0) ths25 (0) ths24 (0) 699 c99 frm_pr58 r/w ths23 (0) ths22 (0) ths21 (0) ths20 (0) ths19 (0) ths18 (0) ths17 (0) ths16 (0) 69a c9a frm_pr59 r/w ths15 (0) ths14 (0) ths13 (0) ths12 (0) ths11 (0) ths10 (0) ths9 (0) ths8 (0) 69b c9b frm_pr60 r/w ths7 (0) ths6 (0) ths5 (0) ths4 (0) ths3 (0) ths2 (0) ths1 (0) ths0 (0) 69c c9c frm_pr61 r/w rhs31 (0) rhs30 (0) rhs29 (0) rhs28 (0) rhs27 (0) rhs26 (0) rhs25 (0) rhs24 (0) 69d c9d frm_pr62 r/w rhs23 (0) rhs22 (0) rhs21 (0) rhs20 (0) rhs19 (0) rhs18 (0) rhs17 (0) rhs16 (0) 69e c9e frm_pr63 r/w rhs15 (0) rhs14 (0) rhs13 (0) rhs12 (0) rhs11 (0) rhs10 (0) rhs9 (0) rhs8 (0) 69f c9f frm_pr64 r/w rhs7 (0) rhs6 (0) rhs5 (0) rhs4 (0) rhs3 (0) rhs2 (0) rhs1 (0) rhs0 (0) 6a0 ca0 frm_pr65 r/w reserved (0) reserved (0) reserved (0) reserved (0) reserved (0) reserved (0) tchidts (0) tbyoff6 (0) 6a1 ca1 frm_pr66 r/w reserved (0) reserved (0) reserved (0) reserved (0) reserved (0) reserved (0) rchidts (0) rbyoff6 (0) 6a2 ca2 frm_pr67 reserved reserved reserved reserved reserved reserved reserved reserved 6a3 ca3 frm_pr68 reserved reserved reserved reserved reserved reserved reserved reserved 6a4 ca4 frm_pr69 r/w gptrn3 (0) gptrn2 (0) gptrn1 (0) gptrn0 (0) gfrmsel (0) gblksel (0) tpei (0) itd (0) 6a5 ca5 frm_pr70 r/w dptrn3 (0) dptrn2 (0) dptrn1 (0) dptrn0 (0) duftp (0) dblksel (0) reserved (0) ird (0) 6a6 ca6 lucent technologies inc. 205 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. register maps (continued) transmit signaling registers (read/write) table 204. transmit signaling registers map * in the normal ds1 robbed-bit signaling modes, these bits define the corresponding receive channel signaling mode and are copi ed into the received signaling registers. in the cept signaling modes, these bits are ignored. ? these bits contain unknown data. ? in ds1 4-state and 2-state signaling modes, these bits contain unknown data. in ds1 2-state signaling mode, these bits contain unknown data. ** in the cept signaling modes, the a-, b-, c-, d-, and p-bit information of these registers contains unknown data. ?? in the ds1 signaling modes, these registers contain unknown data. ?? signifies known data. transmit signaling read (r) write (w) bit 7 bit 6 * bit 5 * bit 4 ? bit 3 ? bit 2 ? bit 1 bit 0 register address (hexadecimal) framer 1 framer 2 frm_tsr0 ** r/w p g_0 f_0 d_0 c_0 b_0 a_0 6e0 ce0 frm_tsr1 r/w p g_1 f_1 d_1 c_1 b_1 a_1 6e1 ce1 frm_tsr2 r/w p g_2 f_2 d_2 c_2 b_2 a_2 6e2 ce2 frm_tsr3 r/w p g_3 f_3 d_3 c_3 b_3 a_3 6e3 ce3 frm_tsr4 r/w p g_4 f_4 d_4 c_4 b_4 a_4 6e4 ce4 frm_tsr5 r/w p g_5 f_5 d_5 c_5 b_5 a_5 6e5 ce5 frm_tsr6 r/w p g_6 f_6 d_6 c_6 b_6 a_6 6e6 ce6 frm_tsr7 r/w p g_7 f_7 d_7 c_7 b_7 a_7 6e7 ce7 frm_tsr8 r/w p g_8 f_8 d_8 c_8 b_8 a_8 6e8 ce8 frm_tsr9 r/w p g_9 f_8 d_8 c_8 b_8 a_8 6e9 ce9 frm_tsr10 r/w p g_10 f_10 d_10 c_10 b_10 a_10 6ea cea frm_tsr11 r/w p g_11 f_11 d_11 c_11 b_11 a_11 6eb ceb frm_tsr12 r/w p g_12 f_12 d_12 c_12 b_12 a_12 6ec cec frm_tsr13 r/w p g_13 f_13 d_13 c_13 b_13 a_13 6ed ced frm_tsr14 r/w p g_14 f_14 d_14 c_14 b_14 a_14 6ee cee frm_tsr15 r/w p g_15 f_15 d_15 c_15 b_15 a_15 6ef cef frm_tsr16 ** r/w p g_16 f_16 d_16 c_16 b_16 a_16 6f0 cf0 frm_tsr17 r/w p g_17 f_17 d_17 c_17 b_17 a_17 6f1 cf1 frm_tsr18 r/w p g_18 f_18 d_18 c_18 b_18 a_18 6f2 cf2 frm_tsr19 r/w p g_19 f_19 d_19 c_19 b_19 a_19 6f3 cf3 frm_tsr20 r/w p g_20 f_20 d_20 c_20 b_20 a_20 6f4 cf4 frm_tsr21 r/w p g_21 f_21 d_21 c_21 b_21 a_21 6f5 cf5 frm_tsr22 r/w p g_22 f_22 d_22 c_22 b_22 a_22 6f6 cf6 frm_tsr23 r/w p g_23 f_23 d_23 c_23 b_23 a_23 6f7 cf7 frm_tsr24 ?? r/w p x ?? x d_24 c_24 b_24 a_24 6f8 cf8 frm_tsr25 ?? r/w p x x d_25 c_25 b_25 a_25 6f9 cf9 frm_tsr26 ?? r/w p x x d_26 c_26 b_26 a_26 6fa cfa frm_tsr27 ?? r/w p x x d_27 c_27 b_27 a_27 6fb cfb frm_tsr28 ?? r/w p x x d_28 c_28 b_28 a_28 6fc cfc frm_tsr29 ?? r/w p x x d_29 c_29 b_29 a_29 6fd cfd frm_tsr30 ?? r/w p x x d_30 c_30 b_30 a_30 6fe cfe frm_tsr31 ?? r/w p x x d_31 c_31 b_31 a_31 6ff cff preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 206 lucent technologies inc. lucent technologies inc. register maps (continued) facility data link parameter/control and status registers (read-write) table 205. facility data link register map transmit signaling clear- on-read (cor) read (r) write (w) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register address (hexadecimal) framer 1 framer 2 fdl_pr0 r/w fransit3 (1) fransit2 (0) fransit1 (1) fransit0 (0) reserved (0) reserved (0) flags (0) fdint (0) 800 e00 fdl_pr1 r/w ftprm (0) frpf (0) ftr (0) frr (0) fte (0) fre (0) fllb (0) frlb (0) 801 e01 fdl_pr2 r/w ftbcrc (0) friie (0) frovie (0) freofie (0) frfie (0) ftundie (0) fteie (0) ftdie (0) 802 e02 fdl_pr3 r/w ftfc (0) ftabt (0) ftil5 (0) ftil4 (0) ftil3 (0) ftil2 (0) ftil1 (0) ftil0 (0) 803 e03 fdl_pr4 r/w ftd7 (0) ftd6 (0) ftd5 (0) ftd4 (0) ftd3 (0) ftd2 (0) ftd1 (0) ftd0 (0) 804 e04 fdl_pr5 r/w ftic7 (0) ftic6 (0) ftic5 (0) ftic4 (0) ftic3 (0) ftic2 (0) ftic1 (0) ftic0 (0) 805 e05 fdl_pr6 r/w fransie (0) reserved (0) fril5 (0) fril4 (0) fril3 (0) fril2 (0) fril1 (0) fril0 (0) 806 e06 fdl_pr7 reserved reserved reserved reserved reserved reserved reserved reserved reserved fdl_pr8 r/w frmc7 (0) frmc6 (0) frmc5 (0) frmc4 (0) frmc3 (0) frmc2 (0) frmc1 (0) frmc0 (0) 808 e08 fdl_pr9 r/w reserved (0) ftm (0) fmatch (0) faloct (0) fmstat (0) foctof2 (0) foctof 1 (0) foctof0 (0) 809 e09 fdl_pr10 r/w ftansi (0) reserved (0) ftansi5 (0) ftansi4 (0) ftansi3 (0) ftansi2 (0) ftansi1 (0) ftansi0 (0) 80a e0a fdl_sr0 cor fransi fridl froveru n freof frf ftunda bt ftem ftdone 80b e0b fdl_sr1 r fted ftqs6 ftqs5 ftqs4 ftqs3 ftqs2 ftqs1 ftqs0 80c e0c fdl_sr2 r freof frqs6 frqs5 frqs4 frqs3 frqs2 frqs1 frqs0 80d e0d fdl_sr3 r 0 0 x5 x4 x3 x2 x1 x0 80e e0e fdl_sr4 r frd7 (0) frd6 (0) frd5 (0) frd4 (0) frd3 (0) frd2 (0) frd1 (0) frd0 (0) 807 e07 lucent technologies inc. 207 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. absolute maximum ratings stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are abso- lute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. operating conditions handling precautions although protection circuitry has been designed into this device, proper precautions should be taken to avoid expo- sure to electrostatic discharge (esd) during handling and mounting. lucent employs a human-body model (hbm) and charged-device model (cdm) for esd-susceptibility testing and protection design evaluation. esd voltage thresholds are dependent on the circuit parameters used in the defined model. no industry wide standard has been adopted for the cdm. however, a standard hbm (resistance = 1500 w , capacitance = 100 pf) is widely used and, therefore, can be used for comparison purposes. the hbm esd threshold presented here was obtained by using these circuit parameters. table 206. esd threshold voltage parameter symbol min max unit v dd supply voltage range v dd C0.5 7 v maximum voltage (digital pins) with respect to v dd 0.3v minimum voltage (digital pins) with respect to grnd C0.3 v maximum allowable voltages (rtip, rring) with respect to v dd 0.5v minimum allowable voltages (rtip, rring) with respect to grnd C0.5 v storage temperature range t stg C65 125 c parameter symbol min typ max unit power supply v dd 4.75 5.0 5.25 v power dissipation p d 500 750 mw ambient temperature t a C40 85 c device voltage T7630 >1000 v preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 208 lucent technologies inc. lucent technologies inc. electrical characteristics logic interface characteristics table 207. logic interface characteristics (t a = C40 c to +85 c, v dd = 5.0 v 5%, v ss = 0) * sinking. ? sourcing. ? 100 pf allowed for ad[7:0] (pins 86 to 79) and a[11:0] (pins 98 to 87). notes: all buffers use ttl levels. all inputs are driven between 2.4 v and 0.4 v. an internal 50 k w pull-up is provided on the 3-state , reset , ds1/cept , framer , sysclk, cksel , mpmode, mpmux, cs , mpclk, jtagtdi, jtagtck, and jtagtms pins. an internal 50 k w pull-down is provided on the jtagrst pin. power supply bypassing external bypassing is required for each channel. a 1.0 m f capacitor must be connected between v dd x and grndx. in addition, a 0.1 m f capacitor must be connected between v dd and grnd, and a 0.1 m f capacitor must be connected between v dda and grnd a . ground plane connections are required for grndx, grnd, and grnd a . power plane connections are also required for v dd x and v dd . the need to reduce high-frequency cou- pling into the analog supply (v dda ) may require an inductive bead to be inserted between the power plane and the v dda pin of each channel. capacitors used for power supply bypassing should be placed as close as possible to the device pins for maximum effectiveness. parameter symbol test conditions min max unit input voltage: low high v il v ih i il = C70 a* i ih = 10 a ? 0 2.1 0.8 v dd v v input leakage i l 10a output voltage: low high v ol v oh i ol = C5.0 ma* i oh = 5.0 ma ? 0 v dd C 0.5 0.4 v dd v v input capacitance c i 3.0pf load capacitance ? c l 50 pf lucent technologies inc. 209 preliminary data sheet october 2000 T7630 dual t1/e1 5.0 v short-haul terminator (terminator-ii) lucent technologies inc. outline diagram 144-pin tqfp dimensions are in millimeters. 5-3815(f)r.6 detail a 0.45/0.75 gage plane seating plane 1.00 ref 0.25 detail b 0.19/0.27 0.08 m 0.106/0.200 1.60 max seating plane 0.08 0.50 typ 1.40 0.05 0.05/0.15 detail a detail b pin #1 identifier zone 20.00 0.20 22.00 0.20 109 144 1 36 37 72 73 108 20.00 0.20 22.00 0.20 preliminary data sheet T7630 dual t1/e1 5.0 v short-haul terminator (terminator ii) october 2000 lucent technologies inc. reserves the right to make changes to the product(s) or information contained herein without notice. n o liability is assumed as a result of their use or application. no rights under any patent accompany the sale of any such product(s) or information. slc is a registered trademark of lucent technologies. copyright ? 2000 lucent technologies inc. all rights reserved october 2000 ds00-191tic (replaces ds98-234tic) for additional information, contact your microelectronics group account manager or the following: internet: http://www.lucent.com/micro , or for fpga information, http://www.lucent.com/orca e-mail: docmaster@micro.lucent.com n. america: microelectronics group, lucent technologies inc., 555 union boulevard, room 30l-15p-ba, allentown, pa 18109-3286 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia pacific: microelectronics group, lucent technologies singapore pte. ltd., 77 science park drive, #03-18 cintech iii, singap ore 118256 tel. (65) 778 8833 , fax (65) 777 7495 china: microelectronics group, lucent technologies (china) co., ltd., a-f2, 23/f, zao fong universe building, 1800 zhong shan xi road, shanghai 200233 p. r. china tel. (86) 21 6440 0468 , ext. 325 , fax (86) 21 6440 0652 japan: microelectronics group, lucent technologies japan ltd., 7-18, higashi-gotanda 2-chome, shinagawa-ku, tokyo 141, japan tel. (81) 3 5421 1600 , fax (81) 3 5421 1700 europe: data requests: microelectronics group dataline: tel. (44) 7000 582 368 , fax (44) 1189 328 148 technical inquiries: germany: (49) 89 95086 0 (munich), united kingdom: (44) 1344 865 900 (ascot), france: (33) 1 40 83 68 00 (paris), sweden: (46) 8 594 607 00 (stockholm), finland: (358) 9 3507670 (helsinki), italy: (39) 02 6608131 (milan), spain: (34) 1 807 1441 (madrid) ordering information device code package temperature comcode (ordering number) t - 7630 - - - tl - db 144-pin tqfp C40 c to +85 c 107913337 |
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